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Patent # Description
US-9,331,070 Variable capacitor and integrated circuit including the same
There are provided a variable capacitor and an integrated circuit (IC) including the variable capacitor. The variable capacitor includes: a plurality of...
US-9,331,069 Resistor memory bit-cell and circuitry and method of making the same
A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching...
US-9,331,068 Hybrid wide-bandgap semiconductor bipolar switches
A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor...
US-9,331,067 BigFET ESD protection that is robust against the first peak of a system-level pulse
Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD...
US-9,331,066 Method and computer-readable medium for detecting parasitic transistors by utilizing equivalent circuit and...
A method of detecting a parasitic transistor detecting is provided. The method includes extracting several diodes from a selected area, selecting at least one...
US-9,331,065 Semiconductor diode and method of manufacture
A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the...
US-9,331,064 Fin diode structure
A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity...
US-9,331,063 Semiconductor device
A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting...
US-9,331,062 Integrated circuits with backside power delivery
Integrated circuits with backside power delivery capabilities are provided. An integrated circuit may include a substrate having front and back surfaces, a...
US-9,331,061 Parallel connection methods for high performance transistors
Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located...
US-9,331,060 Device including two power semiconductor chips and manufacturing thereof
A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face....
US-9,331,059 Chip, chip package and die
In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated...
US-9,331,058 Package with SoC and integrated memory
A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The...
US-9,331,057 Semiconductor device
A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An...
US-9,331,056 White LED assembly with LED string and intermediate node substrate terminals
A white LED assembly includes a string of series-connected blue LED dice mounted on a substrate. The substrate has a plurality of substrate terminals. A first...
US-9,331,055 Semiconductor package and method for fabricating the same
A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip...
US-9,331,054 Semiconductor package assembly with decoupling capacitor
A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach...
US-9,331,053 Stacked semiconductor chip device with phase change material
Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a...
US-9,331,052 Pad configurations for an electronic package assembly
Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening,...
US-9,331,051 Wafer scale technique for interconnecting vertically stacked dies
A method and device for interconnecting stacked die surfaces with electrically conductive traces is provided that includes bonding, using a first layer of a...
US-9,331,050 Localized alloying for improved bond reliability
Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the...
US-9,331,049 Bonding structure of bonding wire
The invention is aimed at providing a bonding structure of a copper-based bonding wire, realizing low material cost, high productivity in a continuous bonding...
US-9,331,048 Bonded stacked wafers and methods of electroplating bonded stacked wafers
A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second...
US-9,331,047 Mounting method and mounting structure for semiconductor package component
A semiconductor package component (3) is mounted on a substrate (1) in such a manner that an electrode (2) of the substrate (1) and an electrode of the...
US-9,331,046 Integrated circuit package with voltage distributor
An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of...
US-9,331,045 Semiconductor die laminating device with independent drives
A laminating device (230) and method are disclosed for laminating semiconductor die (220) on substrates on a panel (200) of substrates. The laminating device...
US-9,331,044 Semiconductor device connected by anisotropic conductive film
A semiconductor device connected by an anisotropic conductive film including a first insulation layer, a conductive layer, and a second insulation layer one...
US-9,331,043 Localized sealing of interconnect structures in small gaps
An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the...
US-9,331,042 Semiconductor device manufacturing method and semiconductor device
A plurality of protruding electrodes of a semiconductor chip are in contact with a plurality of electrodes formed on a semiconductor substrate, via a plurality...
US-9,331,041 Semiconductor device and semiconductor device manufacturing method
A semiconductor device includes a semiconductor chip, and a terminal connected with the semiconductor chip. The terminal has a first surface and a second...
US-9,331,040 Manufacture of coated copper pillars
The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area...
US-9,331,039 Semiconductor device including a buffer layer structure for reducing stress
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different...
US-9,331,038 Semiconductor interconnect structure
A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on...
US-9,331,037 Preventing misshaped solder balls
"Thick line dies" that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on...
US-9,331,036 Semiconductor device
In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface...
US-9,331,035 Semiconductor device and method of manufacturing the same
A semiconductor device is provided with: a semiconductor substrate; an insulation film formed above the semiconductor substrate; a pad formed on the insulation...
US-9,331,033 Method for forming stacked metal contact in electrical communication with aluminum wiring in semiconductor...
A method for forming a stacked metal contact in electrical communication with aluminum wiring in a semiconductor wafer of an integrated circuit is disclosed....
US-9,331,032 Hybrid bonding and apparatus for performing the same
A method includes performing a hybrid bonding to bond a first package component to a second package component, so that a bonded pair is formed. In the bonded...
US-9,331,031 Wireless communication system
A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a...
US-9,331,030 Integrated antenna package and manufacturing method thereof
An integrated antenna package including a laminated structure and a multi-layered substrate is provided. The laminated structure includes at least a chip...
US-9,331,029 Microelectronic packages having mold-embedded traces and methods for the production thereof
Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method...
US-9,331,028 Electric field gap device and manufacturing method
Substrate material is oxidized around side walls of a set of channels. A shielding structure means there is more oxide growth at the top than the bottom with...
US-9,331,027 Method for detecting electrical energy produced from a thermoelectric material contained in an integrated circuit
An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body....
US-9,331,026 Methods and apparatus for fabricating capacitor structures with a terminal shield
A capacitor structure having a complete terminal shield is provided. The capacitor structure may include a first conductive segment with a first set of...
US-9,331,025 Die edge sealing structures and related fabrication methods
Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor...
US-9,331,024 IC wafer having electromagnetic shielding effects and method for making the same
An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer...
US-9,331,023 Device packaging
Some embodiments of the present disclosure provide a semiconductive device, including a semiconductive substrate. A conductive pad is on the semiconductive...
US-9,331,022 Substrate and patterning device for use in metrology, metrology method and device manufacturing method
A pattern from a patterning device is applied to a substrate by a lithographic apparatus. The applied pattern includes product features and metrology targets....
US-9,331,021 Chip-on-wafer package and method of forming same
A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past...
US-9,331,020 Electronic interconnects and devices with topological surface states and methods for fabricating same
An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having...
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