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Patent # Description
US-9,331,019 Device comprising a ductile layer and method of making the same
Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment...
US-9,331,018 Semiconductor arrangement and formation thereof
One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement...
US-9,331,017 Chip package incorporating interfacial adhesion through conductor sputtering
This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an...
US-9,331,016 SOC design with critical technology pitch alignment
An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality...
US-9,331,015 Semiconductor device with a multilayer wire
A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the...
US-9,331,014 Tunable power distribution network and method of use thereof
An improved power distribution network comprises a substrate, an integrated circuit mounted on the substrate, first and second tunable decoupling capacitors...
US-9,331,013 Integrated capacitor
A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive...
US-9,331,012 Method for fabricating a physical unclonable interconnect function array
A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over...
US-9,331,011 Electronic component built-in substrate and method of manufacturing the same
An electronic component built-in substrate, includes, a substrate having an opening portion, a first wiring layer formed in the substrate, an electronic...
US-9,331,010 System support for electronic components and method for production thereof
A chip (2, 3) is arranged above a top side of a flexible support (1) and mechanically decoupled from the support. Electrical connections (8, 11) of the chip are...
US-9,331,009 Chip electronic component and method of manufacturing the same
A chip electronic component may be capable of improving connectivity between internal coils formed on upper and lower surfaces of an insulating substrate and...
US-9,331,008 Semiconductor device
The semiconductor device of the present invention includes a semiconductor substrate provided with semiconductor elements, a lower layer wiring pattern which...
US-9,331,007 Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor...
A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of...
US-9,331,006 Semiconductor device
A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also...
US-9,331,005 Power semiconductor package with multi-section conductive carrier
In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor...
US-9,331,004 Magnetically coupled galvanically isolated communication using lead frame
An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within the encapsulation. The lead frame...
US-9,331,003 Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereof
An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead...
US-9,331,002 Semiconductor device and method of forming through vias with reflowed conductive material
A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating...
US-9,331,001 Semiconductor module
A semiconductor module includes a semiconductor device; a metal plate portion that includes a first surface on a side of the semiconductor device and has a...
US-9,331,000 Heat management in electronics packaging
An electronics packaging system includes an insulator that electrically insulates a heat sink from electrical leads. An interface between the insulator and the...
US-9,330,999 Multi-component integrated heat spreader for multi-chip packages
A multi-component heat spreader comprising a top component having a first surface and an opposing second surface with either a cavity extending therein from the...
US-9,330,998 Thermal interface material assemblies and related methods
A thermal interface material assembly generally includes a substrate and one or more pillars protruding outwardly away from the substrate. A ...
US-9,330,997 Heat spreading structures for integrated circuits
A heat spreader structure includes a planar portion and a slanted portion. The slanted portion extends at an angle from an edge of the planar portion. The first...
US-9,330,996 Semiconductor module system, semiconductor module arrangement and method for mounting a semiconductor module on...
A semiconductor module system has a semiconductor module and a protective cover. The semiconductor module has a bottom side with a heat dissipation surface and...
US-9,330,994 Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring
A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die...
US-9,330,993 Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include...
US-9,330,992 Wiring substrate for a semiconductor device having differential signal paths
A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided...
US-9,330,990 Method of endpoint detection of plasma etching process using multivariate analysis
Disclosed is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy...
US-9,330,989 System and method for chemical-mechanical planarization of a metal layer
A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a...
US-9,330,988 Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside...
Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are...
US-9,330,987 Hot spot identification, inspection, and review
A method for identifying, inspecting, and reviewing all hot spots on a specimen is disclosed by using at least one SORIL e-beam tool. A full die on a...
US-9,330,986 Manufacturing method for solar cell and solar cell manufacturing system
The invention includes: a first process of forming a texture structure on both surfaces of a semiconductor substrate of a first conductivity type; a second...
US-9,330,985 Automated hybrid metrology for semiconductor device fabrication
Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor...
US-9,330,984 CMOS fin integration on SOI substrate
A method for complementary metal oxide semiconductor (CMOS) fin integration includes forming fin structures from a semiconductor layer of a silicon-on-insulator...
US-9,330,983 CMOS NFET and PFET comparable spacer width
A method including forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on...
US-9,330,982 Semiconductor device with diffusion barrier film and method of manufacturing the same
A method of forming a diffusion barrier film over fins and the resulting device are provided. Embodiments include forming silicon fins over a substrate;...
US-9,330,981 Semiconductor device and method of manufacturing the same
Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor...
US-9,330,980 Semiconductor process
A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial...
US-9,330,979 LDMOS transistor having elevated field oxide bumps and method of making same
A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the...
US-9,330,978 Semiconductor device
A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor...
US-9,330,977 Hybrid wafer dicing approach using a galvo scanner and linear stage hybrid motion laser scribing process and...
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
US-9,330,976 Wafer processing method
A wafer processing method includes forming a resist film on the front side of a wafer in an area except division lines, plasma etching the wafer to form a...
US-9,330,975 Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate vias
A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides...
US-9,330,974 Through level vias and methods of formation thereof
In one embodiment, a semiconductor device includes a first metal line disposed in a first metal level above a substrate. A second metal line is disposed in a...
US-9,330,973 Workpiece processing method
Disclosed is a method of processing a workpiece so as to form an opening that extends from an oxide region to a base layer through a portion between the raised...
US-9,330,972 Methods of forming contact structures for semiconductor devices and the resulting devices
One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The...
US-9,330,971 Method for fabricating integrated circuits including contacts for metal resistors
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes...
US-9,330,970 Structure and method for high performance interconnect
The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a...
US-9,330,969 Air gap formation between bit lines with top protection
Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial...
US-9,330,968 Method of fabricating integrated circuit
A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a...
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