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Patent # Description
US-9,330,967 Method of fabricating a semiconductor device with reduced leak paths
A method of fabricating a semiconductor device with reduced leak paths is disclosed. The method comprises etching a void in non-conductive material in the...
US-9,330,966 Methods of forming semiconductor devices
Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first...
US-9,330,965 Double self aligned via patterning
A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer;...
US-9,330,964 Semiconductor structures and fabrication methods for improving undercut between porous film and hardmask film
A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a to-be-etched layer made of porous low...
US-9,330,963 Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a...
US-9,330,962 Non-lithographic hole pattern formation
A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound...
US-9,330,961 Stacked protection devices and related fabrication methods
Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a...
US-9,330,960 Semiconductor devices including capacitors
A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a...
US-9,330,959 Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation
An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral...
US-9,330,958 Process for fabricating a heterostructure limiting the formation of defects
The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the...
US-9,330,957 Process for assembling two wafers and corresponding device
A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one...
US-9,330,956 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device is provided and comprises steps as follows. A Si substrate is provided. The Si substrate includes a first...
US-9,330,955 Support ring with masked edge
A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge. The inner edge...
US-9,330,954 Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
Wafer to carrier adhesion without mechanical adhesion for formation of an IC. In such formation, an apparatus has a bottom surface of a substrate abutting a top...
US-9,330,953 Electrostatic chuck device
An electrostatic chuck device (1) according to the invention includes an electrostatic chuck section (2) that has a principal surface as a placement surface on...
US-9,330,952 Bipolar mobile electrostatic carriers for wafer processing
In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode...
US-9,330,951 Robot and adaptive placement system and method
An apparatus including at least one processor; and at least one non-transitory memory including computer program code, the at least one memory and the computer...
US-9,330,950 Substrate processing apparatus
A substrate processing apparatus includes a processing unit performing a predetermined processing on a substrate; a transfer chamber; and a substrate...
US-9,330,949 Heat treatment apparatus for heating substrate by irradiating substrate with flash of light
Three support members made of silicon carbide are provided fixedly on an inner periphery of the support ring. The support members are inclined at an angle in...
US-9,330,948 Heater unit, fan filter unit, and substrate processing apparatus
A heater unit according to an embodiment includes: a flat heater including a linear heating element arranged in a planar pattern; a first mesh body formed in a...
US-9,330,947 Methods for forming package-on-package structures having buffer dams
Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing...
US-9,330,946 Method and structure of die stacking using pre-applied underfill
Structures and processes for die stacking using an opaque or translucent pre-applied underfill material generally include selectively applying a low surface...
US-9,330,945 Integrated circuit package system with multi-chip module
An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a...
US-9,330,944 Bio-implantable hermetic integrated ultra high density device
An implantable bio-compatible integrated circuit device and methods for manufacture thereof are disclosed herein. The device includes a substrate having a...
US-9,330,943 Low cost repackaging of thinned integrated devices
A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive...
US-9,330,942 Semiconductor device with wiring substrate including conductive pads and testing conductive pads
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of...
US-9,330,941 Package carrier and manufacturing method thereof
A manufacturing method of a package carrier is provided. A supporting board having an upper surface which a patterned circuit layer formed thereon is provided....
US-9,330,940 Semiconductor device and manufacturing method thereof
There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased...
US-9,330,939 Method of enabling seamless cobalt gap-fill
Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact...
US-9,330,938 Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly...
US-9,330,937 Etching of semiconductor structures that include titanium-based layers
Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated...
US-9,330,936 Method for depositing metal layers on germanium-containing films using metal chloride precursors
A method is provided for forming a semiconductor device. According to one embodiment, the method includes providing a substrate having a Ge-containing film...
US-9,330,935 Plasma etching method and plasma etching apparatus
Disclosed is a plasma etching method which suppresses the narrowing of the line-width of the line formed by etching and maintain the height of a remaining...
US-9,330,934 Methods of forming patterns on substrates
Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the...
US-9,330,933 Method and apparatus for planarizing a polymer layer
A method for planarizing a polymer layer is provided which includes providing a substrate having the polymer layer formed thereon, providing a structure having...
US-9,330,932 Methods of fabricating features associated with semiconductor substrates
Some embodiments include a method in which a mixture of polynucleotide structures comprises a set of surface shapes. Surface shapes of some polynucleotide...
US-9,330,931 Method of manufacturing semiconductor device
In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a...
US-9,330,930 Plasma etching method and semiconductor device manufacturing method
A plasma etching method for etching a substrate includes an adjustment step adjusting a concentration distribution of active species contained in plasma. The...
US-9,330,929 Systems and methods for horizontal integration of acceleration sensor structures
Embodiments relate to integrated circuit sensors, and more particularly to sensors integrated in an integrated circuit structure and methods for producing the...
US-9,330,928 Methods for selective etching of a multi-layer substrate
A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO.sub.2 or ZrO.sub.2 layer...
US-9,330,927 System, method and apparatus for generating pressure pulses in small volume confined process reactor
A plasma processing system and method includes a processing chamber, and a plasma processing volume included therein. The plasma processing volume having a...
US-9,330,926 Fabrication of a silicon structure and deep silicon etch with profile control
A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine...
US-9,330,925 Thin-film transistor, manufacturing method thereof, and electronic apparatus using thin-film transistor
A thin-film transistor includes a substrate, a gate electrode over the substrate, an insulating layer over the gate electrode, and a semiconductor layer over...
US-9,330,924 Method for forming control gate salicide
A method for forming a semiconductor device includes forming a conductive structure of a silicon material on a substrate and forming a planarized dielectric...
US-9,330,923 Non-volatile memory and method of manufacturing the same
A semiconductor process includes the steps of providing a semiconductor substrate with a logic region and a memory region, defining memory gates on the memory...
US-9,330,922 Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure
A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions,...
US-9,330,921 Semiconductor device and method of manufacturing the same
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a memory cell disposed on the semiconductor substrate. The...
US-9,330,920 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region...
US-9,330,919 Method for manufacturing substrate
A method for manufacturing a substrate is provided. The method includes irradiating a single crystal substrate with a beam of laser or charged particles while...
US-9,330,918 Edge termination by ion implantation in gallium nitride
A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion...
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