Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,330,061 Determination of steering angle for a motor vehicle
Method and control device for determining a steering angle of a motor vehicle, wherein a theoretical steering angle is calculated by a vehicle model and a...
US-9,330,060 Method and device for encoding and decoding video image data
A method and device for encoding and decoding video image data. An MPEG decoding and encoding process using data flow pipeline architecture implemented using...
US-9,330,059 Identifying logical planes formed of compute nodes of a subcommunicator in a parallel computer
In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the...
US-9,330,058 Apparatus, method, system and executable module for configuration and operation of adaptive integrated...
The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable...
US-9,330,057 Reconfigurable processor and mini-core of reconfigurable processor
A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a...
US-9,330,056 Communication protocol placement into switch memory
Direct memory transfer of data from the memory of a server to a memory of a switch. A server identifies a block of data in the memory of the server and a...
US-9,330,055 Modular architecture for extreme-scale distributed processing applications
Embodiments of the present invention relate to a new data center architecture that provides for efficient processing in distributed analytics applications. In...
US-9,330,054 System and method for assigning a message
A processor of a plurality of processors includes a processor core and a message manager. The message manager is in communication with the processor core. The...
US-9,330,053 True push architecture for internet protocol notification
A method of true push for internet protocol notification to a mobile communication device implemented by at least one server computer. The method comprises...
US-9,330,052 Transpose box based network scaling
The deployment and scaling of a network of electronic devices can be improved by utilizing one or more network transpose boxes. Each transpose box can include a...
US-9,330,051 Collection of web server performance metrics to a centralized database for reporting and analysis
Systems, methods, and computer-readable media are provided for, among other things, generating web server performance metrics from log file information and...
US-9,330,050 Deployment wizard
A method and apparatus are provided for collecting deployment information from a user for a multi-tier computer system. The method includes the steps of...
US-9,330,049 Method and apparatuses for monitoring system bus
Embodiments of the present invention provide a method and apparatuses for monitoring a system bus. The method includes: performing, by a monitoring apparatus,...
US-9,330,048 Balancing response times for synchronous I/O requests having different priorities
A computing environment, such as an data mirroring or replication storage system, may need to process synchronous I/O requests having different priorities in...
US-9,330,047 Wireless docking service with direct connection to peripherals
In one example, a method includes receiving, from a user application and with a wireless docking service of a wireless docking communications stack executing on...
US-9,330,046 Portable instrument and docking station with divided universal serial bus communication device
A universal serial bus (USB) communication system includes a portable instrument and a docking station that communicate with a host device using a divided USB...
US-9,330,045 Controller area network (CAN) device and method for controlling CAN traffic
Embodiments of a device and method are disclosed. In an embodiment, a CAN device is disclosed. The CAN device includes a TXD input interface, a TXD output...
US-9,330,044 High-speed data transmission interface circuit and design method of the same
A high-speed data transmission interface circuit used in a network switch device is provided. The high-speed data transmission interface circuit comprises a...
US-9,330,043 Multi-rate, multi-port, gigabit SERDES transceiver
A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to...
US-9,330,042 Determining extended capability of a channel path
A computer program product includes a tangible storage storing instructions for performing a method. The method includes: sending a request from a processing...
US-9,330,041 Staggered island structure in an island-based network flow processor
An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus...
US-9,330,040 Serial configuration of a reconfigurable instruction cell array
A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric...
US-9,330,039 Crosstalk aware encoding for a data bus
Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a...
US-9,330,038 Computer arbitration system, bandwidth, allocation apparatus, and method thereof
The bandwidth allocation apparatus includes a high bandwidth arbitration module, a low bandwidth arbitration module and a multiplexer. The high bandwidth...
US-9,330,037 Dynamically resizing direct memory access (DMA) windows
A dynamic DMA window mechanism can resize DMA windows dynamically by increasing one DMA window at the expense of reducing a neighboring DMA window. The dynamic...
US-9,330,036 Interrupt reduction by dynamic application buffering
Systems and methods are disclosed for processing a queue associated with a request. An example system includes an input/output (I/O) interface that receives a...
US-9,330,035 Method and apparatus for interrupt handling
A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt....
US-9,330,034 Levelization of memory interface for communicating with multiple memory devices
In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal...
US-9,330,033 System, method, and computer program product for inserting a gap in information sent from a drive to a host device
A system, method, and computer program product are provided for inserting a gap in information sent from a drive to a host device. In operation, one or more...
US-9,330,032 Method, apparatus and system for controlling peripheral devices in communication with a playout device using a...
Embodiments of the present invention provide a method, apparatus and system for controlling a peripheral device in communication with a content playout device....
US-9,330,031 System and method for calibration of serial links using a serial-to-parallel loopback
A system and method for calibration of serial links using serial-to-parallel loopback. Embodiments of the present invention are operable for calibrating serial...
US-9,330,030 Bridge decoder for a vehicle infotainment system
An intermediary device may be utilized to form a communication bridge between a vehicle infotainment system and a remote device. The computing device forming...
US-9,330,029 Multiple connector IO board for receiving multiple I/O stream
An apparatus and system for processing I/O from a data storage chassis, the apparatus and system comprising a first I/O printed circuit board (PCB) including...
US-9,330,028 Instruction and logic for a binary translation mechanism for control-flow security
A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the...
US-9,330,027 Register access white listing
A system employs a white list of authorized transactions to control access to system registers. In an embodiment, the white list is loaded into filter registers...
US-9,330,026 Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when...
A security apparatus and method are provided for performing a security algorithm that prevents unauthorized access to contents of a physical address (PA) that...
US-9,330,025 Information processing apparatus, memory control apparatus, and control method thereof
A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus...
US-9,330,024 Processing device and method thereof
A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a...
US-9,330,023 Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels...
For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual...
US-9,330,022 Power logic for memory address conversion
In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated...
US-9,330,021 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-9,330,020 System, apparatus, and method for transparent page level instruction translation
Detailed herein are systems, apparatuses, and methods for transparent page level instruction translation. Exemplary embodiments include an instruction...
US-9,330,018 Suppressing virtual address translation utilizing bits and instruction tagging
Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a...
US-9,330,017 Suppressing virtual address translation utilizing bits and instruction tagging
A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical...
US-9,330,016 Systems and methods for managing read-only memory
Embodiments for managing read-only memory. A system includes a memory device including a real memory and a tracking mechanism configured to track relationships...
US-9,330,015 Identification of low-activity large memory pages
Large pages that may impede memory performance in computer systems are identified. In operation, mappings to selected large pages are temporarily demoted to...
US-9,330,014 Method and system for full resolution real-time data logging
A method and data-logging system are provided. The system includes a map-ahead thread configured to acquire blocks of private memory for storing data to be...
US-9,330,013 Method of cloning data in a memory for a virtual machine, product of computer programs and computer system...
A method of cloning data in a memory for a source virtual machine (VM) and at least one cloned virtual machine is proposed. A mapping relationship between a...
US-9,330,012 Allocation enforcement in a multi-tenant cache mechanism
Cache optimization. Cache access rates for tenants sharing the same cache are monitored to determine an expected cache usage. Factors related to cache...
US-9,330,011 Microprocessor with integrated NOP slide detector
A microprocessor includes an instruction cache and a hardware state machine configured to detect a no operation (NOP) slide by counting a continuous sequence of...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.