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Patent # Description
US-9,337,875 Method and apparatus for reducing charge and discharge time of capacitive elements
A system that incorporates teachings of the subject disclosure may include, for example, emulating a behavior of an RF capacitive device utilizing a mirror...
US-9,337,874 High-speed digital signal processing systems
Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment,...
US-9,337,873 Miscorrection detection for error correcting codes using bit reliabilities
Miscorrection detection for error correction codes using bit reliabilities includes receiving a plurality of reliabilities corresponding to respective ones of a...
US-9,337,872 Configurable, error-tolerant memory control
Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each...
US-9,337,871 Method and apparatus for processing data
Embodiments of the present invention provide a method and an apparatus for processing data. The method includes: performing code block segmentation on a data...
US-9,337,869 Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same
An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of:...
US-9,337,868 Iterative decoding for cascaded LDPC and TCM coding
At a receiver side, to enhance the performance of concatenated LDPC and TCM coding, an iterative decoding between TCM decoder and LDPC decoder enables...
US-9,337,867 Cyclic decoding for cascaded forward error-correction FEC codes
A computer implemented method for a cyclic (forward-backward) decoding for a forward error-correction FEC scheme includes decoding a given k-1.sub.th codeword...
US-9,337,866 Apparatus for processing signals carrying modulation-encoded parity bits
A receiver configured for use in a communication system, such as a magnetic recording channel, and having a soft-output channel detector provided with a...
US-9,337,865 Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders
Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword...
US-9,337,864 Non-binary LDPC decoder using binary subgroup processing
In one embodiment, an electronic system includes a decoder configured to decode an encoded data unit using multiple variable nodes and multiple check nodes to...
US-9,337,863 Methods and apparatus for rational compression and decompression of numbers
Methods and apparatus are provided for rational compression of numbers. One or more numbers are compressed by obtaining a plurality of numbers (e.g., integer...
US-9,337,862 VLSI efficient Huffman encoding apparatus and method
A compression algorithm based on Huffman coding is disclosed that is adapted to be readily implemented using VLSI design. A data file may be processed to...
US-9,337,861 Method and system for generating a data set
Systems, methods, and stored coded instruction sets for reducing the amount of data captured, i.e., retained, by a computerized system, such as an aircraft...
US-9,337,860 Precision sub-RADIX2 DAC with analog weight based calibration
A system includes a sub-binary radix digital-to-analog converter (DAC) that converts a digital input signal to an analog output signal based on a sub-radix DAC...
US-9,337,859 Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture
Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels...
US-9,337,858 Data processing system
The present invention provides a data processing system which can increase resolution and which has excellent tracking with respect to the switching of a...
US-9,337,857 Analog conversion device and programmable controller system
An analog conversion device includes an analog-to-digital (A/D) converter; a shared memory that has an A/D conversion-value storage area for storing the...
US-9,337,856 Calibration for a single ramp multi slope analog-to-digital converter
Methods and Systems for calibrating a Single Ramp Multiple Slope Analog to Digital Converter (SRMS ADC), the ADC including a counter and a plurality N of charge...
US-9,337,855 Digital calibration of transmit digital to analog converter full scale current
A method and apparatus for a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference...
US-9,337,854 Methods and systems for addressing component mismatch in digital-to-analog converters
Present disclosure describes an improved mechanism for addressing component mismatch in a DAC. The mechanism is based on carefully selecting the first DAC unit...
US-9,337,853 Interleaved A/D converter
It is a problem that each ADC sampling circuit connected in parallel in an interleaved ADC releases an electric charge depending on an input signal when...
US-9,337,852 Removing deterministic phase errors from fractional-N PLLs
Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two...
US-9,337,851 Phase locked loop circuit equipped with unity gain bandwidth adjustment
An electronic circuit is described in which a charge pump-based digital phase locked loop circuit is augmented with additional circuitry to monitor and control...
US-9,337,850 All-digital phase-locked loop (ADPLL) with reduced settling time
Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the...
US-9,337,849 Phase detector, phase-frequency detector, and digital phase locked loop
A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a...
US-9,337,848 Clock and data recovery device
A clock and data recovery device is provided which includes a phase detector, a charge pump unit, a loop filter unit, and a voltage controlled oscillator. The...
US-9,337,847 Oscillator
An oscillator used in RF system. The oscillator includes a pair of transistors to which source terminals are interconnected and to which drain and gate...
US-9,337,846 Methods and systems for determining whether a receiver is present on a PCI-express bus
A method for detecting a receiver on a computer bus, comprises the steps of: applying a low voltage state on transmission lines of the computer bus using a...
US-9,337,845 Solving constraint satisfaction problems using a field programmable gate array
A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions,...
US-9,337,844 Generalized parallel counter structures in logic devices
Generalized parallel counter circuitry is configured from logic elements--e.g., on a programmable integrated circuit device. Each logic element includes a logic...
US-9,337,843 Programmable logic device and semiconductor device
Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between...
US-9,337,842 Low voltage differential signaling (LVDS) driving circuit
An LVDS (Low Voltage Differential Signaling) driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first...
US-9,337,841 Circuits for and methods of providing voltage level shifting in an integrated circuit device
A circuit for providing voltage level shifting in an integrated circuit includes an inverter having an input coupled to receive an input signal having a first...
US-9,337,840 Voltage level shifter and systems implementing the same
According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage...
US-9,337,839 Pre-driver and power circuit including the same
Disclosed are a pre-driver having a modified circuit for gate pulse modulation and a power circuit including the same. The pre-driver includes a level shifter...
US-9,337,838 Programmable circuit device and configuration information restoration method
In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and...
US-9,337,837 Physical unclonable function generation and management
Methods, systems and devices related to authentication of chips using physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of...
US-9,337,836 Method for driving semiconductor device
A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for...
US-9,337,835 Controlling a flash device having time-multiplexed, on-die-terminated signaling interface
An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling...
US-9,337,834 CMOS input buffer circuit
A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from...
US-9,337,833 Driven shield for shaping an electric field of a touch sensor
In one embodiment, a method comprises generating, by a control unit, a first drive signal and a second drive signal. The method further includes emitting, by a...
US-9,337,832 Proximity switch and method of adjusting sensitivity therefor
A vehicle proximity switch and method are provided having sensitivity control. The switch includes a proximity sensor, such as a capacitive sensor, installed in...
US-9,337,831 Capacitive wire sensing for furniture
A system and method for incorporating presence-sensing technology into furniture is provided. More particularly, the invention relates to incorporating a...
US-9,337,830 Apparatus and method for processing virtual world
A virtual world processing apparatus and method. Information on sensor capability is converted to binary data and then transmitted, or converted to eXtensible...
US-9,337,829 Electronic device with body-biasing circuit for portable equipment with USB connector for headset
An electronic USB or similar device 101 with a CMOS audio output stage 105 for driving, in a first mode, e.g., a headset via a port commonly used also in a...
US-9,337,828 Transistor including reentrant profile
A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more...
US-9,337,827 Electronic circuit with a reverse-conducting IGBT and gate driver circuit
An electronic circuit includes a reverse-conducting IGBT and a driver circuit. A first diode emitter efficiency of the reverse-conducting IGBT at a first...
US-9,337,826 Semiconductor device and electronic device
To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch...
US-9,337,825 Power switch acceleration scheme for fast wakeup
A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power...
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