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Patent # Description
US-9,337,372 Photovoltaic device
A photovoltaic device may be provided having a semiconductor substrate, an i-type amorphous layer or an i-type amorphous layer formed over a front surface or a...
US-9,337,371 Cam turntable, sun-tracking device equipped with same and control method for the device
Provided are a cam turntable (2), a sun-tracking device equipped with the cam turntable (2) and a control method for the device. The sun-tracking device...
US-9,337,370 Apparatus and method for the automatic assembly of photovoltaic panels
Apparatus and method for the automatic assembly of photovoltaic panels with back-contact architecture, the apparatus comprising a series of six stations that...
US-9,337,369 Solar cells with tunnel dielectrics
A solar cell can have a first dielectric formed over a first doped region of a silicon substrate. The solar cell can have a second dielectric formed over a...
US-9,337,368 Ceramic composition having dispersion of nano-particles therein and methods of fabricating same
Ceramic compositions having a dispersion of nano-particles therein and methods of fabricating ceramic compositions having a dispersion of nano-particles therein...
US-9,337,367 Multiple-junction photoelectric device and its production process
A multiple-junction photoelectric device includes sequentially, a substrate, a first conducting layer, at least two elementary photoelectric devices, at least...
US-9,337,366 Textured optoelectronic devices and associated methods of manufacture
Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state...
US-9,337,365 Transversely-illuminated high current photoconductive switches with geometry-constrained conductivity path
A photoconductive switch having a wide bandgap semiconductor material substrate between opposing electrodes, with one of the electrodes having an aperture or...
US-9,337,364 Solid-state imaging element and electronic apparatus
A solid-state imaging element includes a light receiving unit formed on a semiconductor base, and an anti-reflection film formed on the light receiving unit....
US-9,337,363 Low resistance, low reflection, and low cost contact grids for photovoltaic cells
The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as...
US-9,337,362 Conductive composition and conductive feature formed at low temperatures
A method for forming a conductive feature. The method includes providing a substrate and providing a conductive composition. The conductive composition includes...
US-9,337,361 Photoelectric conversion device and manufacturing method thereof
In a method for manufacturing a photoelectric conversion device, a method for forming an embedded electrode is provided, which is suitable for a groove with a...
US-9,337,360 Non-alloyed contacts for III-V based solar cells
A multi junction solar cell is provided with a non-alloyed ohmic contact metallization stack by inversion of the top semiconductor layer from n-type to p-type...
US-9,337,359 Solar cell and method for manufacturing the same
A method for manufacturing a solar cell may include forming an emitter region that forms a p-n junction with a semiconductor substrate of a first conductive...
US-9,337,358 Photovoltaic cell with benzodithiophene-containing polymer
Benzodithiophene-containing polymers, as well as related photovoltaic cells, articles, systems, and methods, are disclosed.
US-9,337,357 Bifacial solar cell module
A bifacial solar cell module includes a solar cell panel including a plurality of strings arranged in a row direction. Each of the plurality of strings is...
US-9,337,356 Devices and methods related to electrostatic discharge protection benign to radio-frequency operation
Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and...
US-9,337,355 Voltage nonlinear resistor and multilayer varistor using same
A voltage nonlinear resistor includes a plurality of N-type ZnO crystal grains, a grain boundary layer, and an oxide grain as a P-type semiconductor. The grain...
US-9,337,354 Top port MEMS cavity package and method of manufacture thereof
A method for the manufacture of a package encasing a Micro-Electro-Mechanical Systems (MEMS) device provides a cover having a lid and sidewalls with a port...
US-9,337,353 Semiconductor device and method for fabricating the same
A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the...
US-9,337,352 Floating gate flash memory device and compilation method thereof
The present invention discloses a floating gate flash memory device, comprising: a P-type substrate which has a source and a drain, and a first polysilicon...
US-9,337,351 Three-dimensional nonvolatile memory devices including interposed floating gates
Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating...
US-9,337,350 Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of...
A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned...
US-9,337,349 Thin film transistor with a ring-shaped hole of a stopper layer and pixel structure having the thin film transistor
A thin film transistor including a gate, a channel, a stopper layer, a source and a drain is provided. The channel and the gate are overlapped. The stopper...
US-9,337,347 Oxide semiconductor element and semiconductor device
A semiconductor element having high mobility, which includes an oxide semiconductor layer having crystallinity, is provided. The oxide semiconductor layer...
US-9,337,346 Array substrate and method of fabricating the same
An array substrate for an electronic display includes a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; an oxide...
US-9,337,345 Semiconductor device including multilayer wiring layer
The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a...
US-9,337,344 Semiconductor device and manufacturing method thereof
To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a...
US-9,337,343 Semiconductor device, driver circuit, and display device
To provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with...
US-9,337,342 Semiconductor device and method for manufacturing semiconductor device
In a semiconductor device including an oxide semiconductor, the amount of oxygen vacancies is reduced. Moreover, electrical characteristics of a semiconductor...
US-9,337,341 Semiconductor device having aluminum-containing layer between two curved substrates
The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature....
US-9,337,340 FinFET with active region shaped structures and channel separation
A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown...
US-9,337,339 Metal oxide semiconductor device and method for forming the same
The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed...
US-9,337,338 Tucked active region without dummy poly for performance boost and variation reduction
In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation...
US-9,337,337 MOS device having source and drain regions with embedded germanium-containing diffusion barrier
An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the...
US-9,337,336 Replacement metal gates to enhance tranistor strain
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
US-9,337,335 Structure and method to form localized strain relaxed SiGe buffer layer
A method includes forming a multilayered structure by providing a substrate having a semiconductor layer disposed on a top surface thereof, the semiconductor...
US-9,337,334 Semiconductor memory device employing a ferromagnetic gate
A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire....
US-9,337,333 Transistors with an extension region having strips of differing conductivity type
A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions...
US-9,337,332 III-Nitride insulating-gate transistors with passivation
A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor...
US-9,337,331 Semiconductor device
A semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type...
US-9,337,330 Scheme to align LDMOS drain extension to moat
An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a...
US-9,337,329 Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source
A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body...
US-9,337,328 Super-junction trench MOSFETs with closed cell layout
A super-junction trench MOSFET with closed cell layout is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell. Trenched...
US-9,337,327 Manufacturing method of semiconductor device and semiconductor device
The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region...
US-9,337,326 Compound semiconductor device and method for fabricating the same
A first GaN layer (2), a first AlGaN layer (3), a second GaN layer (4) and a third GaN layer (5) are formed in layers on a substrate (1). A second AlGaN layer...
US-9,337,325 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride...
US-9,337,324 Bipolar transistor, band-gap reference circuit and virtual ground reference circuit
The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap...
US-9,337,323 Trench isolation for bipolar junction transistors in BiCMOS technology
Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a...
US-9,337,322 Thin-film transistor and method for manufacturing the same
According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a...
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