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Patent # Description
US-9,337,321 Semiconductor device and method for manufacturing the same
A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device...
US-9,337,320 Method of manufacturing zinc oxide thin film, method of manufacturing thin film transistor, zinc oxide thin...
A method of manufacturing a zinc oxide thin film includes: immersing a base having a conductive portion in at least part of the base, in a solution containing...
US-9,337,319 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device includes a fin-shaped semiconductor layer disposed on a semiconductor substrate, a first insulating film disposed around the fin-shaped...
US-9,337,318 FinFET with dummy gate on non-recessed shallow trench isolation (STI)
An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI)...
US-9,337,317 Semiconductor device including finFET and diode having reduced defects in depletion region
A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first...
US-9,337,316 Method for FinFET device
Provided is a method of forming a fin field effect transistor (FinFET). The method includes forming a fin on a substrate, the fin having a channel region...
US-9,337,315 FinFET spacer formation by oriented implantation
A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed...
US-9,337,314 Technique for selectively processing three dimensional device
A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate...
US-9,337,313 Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same
A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator...
US-9,337,312 Method for system for manufacturing TFT, TFT, and array substrate
The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned...
US-9,337,311 Electronic component, a semiconductor wafer and a method for producing an electronic component
An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending...
US-9,337,310 Low leakage, high frequency devices
Low leakage, high frequency devices and methods of manufacture are disclosed. The method of forming a device includes implanting a lateral diffusion drain...
US-9,337,309 Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels
An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes...
US-9,337,308 Semiconductor device and method for forming the same
A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a...
US-9,337,307 Method for fabricating transistor with thinned channel
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The...
US-9,337,306 Multi-phase source/drain/gate spacer-epi formation
Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a...
US-9,337,305 Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and...
A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region...
US-9,337,304 Method of making semiconductor device
A method of fabricating a semiconductor device includes epitaxially-growing a strained material in a cavity of a substrate comprising a major surface and the...
US-9,337,303 Metal gate stack having TiAICN as work function layer and/or blocking/wetting layer
A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of...
US-9,337,302 On-SOI integrated circuit comprising a subjacent protection transistor
An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel,...
US-9,337,301 Aluminum nitride based semiconductor devices
Semiconductor structures and techniques are described which enable forming aluminum nitride (AIN) based devices by confining carriers in a region of AIN by...
US-9,337,300 Nitride-based semiconductor device
A semiconductor device according to an embodiment includes a nitride semiconductor layer, a gate electrode provided above the nitride semiconductor layer, a...
US-9,337,299 Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p-...
US-9,337,298 Silicon carbide semiconductor device and method for producing the same
In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion...
US-9,337,297 Fringe capacitance reduction for replacement gate CMOS
A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls...
US-9,337,296 Integrated circuits having a metal gate structure and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating an integrated circuit...
US-9,337,295 Semiconductor devices and methods of manufacturing the same
Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate...
US-9,337,294 Semiconductor device fabrication method and semiconductor device
There is provided a method of fabricating a semiconductor device, the method including: forming a first semiconductor region at a front surface of a substrate,...
US-9,337,293 Semiconductor device having electrode and manufacturing method thereof
The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a...
US-9,337,292 Very high aspect ratio contact
A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the...
US-9,337,291 Deep gate-all-around semiconductor device having germanium or group III-V active layer
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes...
US-9,337,290 Layout architecture for performance improvement
An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a...
US-9,337,289 Replacement gate MOSFET with a high performance gate electrode
In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the...
US-9,337,288 Method of manufacturing MOS-type semiconductor device
A method of manufacturing a MOS-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power...
US-9,337,287 Non-volatile memory device
A non-volatile memory device includes an isolation layer formed over a substrate to define an active region, a floating gate formed over the substrate, a...
US-9,337,285 Contact structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a...
US-9,337,284 Closed cell lateral MOSFET using silicide source and body regions
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion...
US-9,337,283 Semiconductor device with field plate
A semiconductor device includes a first semiconductor layer, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer,...
US-9,337,282 Semiconductor device with point defect region doped with transition metal
A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma...
US-9,337,281 Planar semiconductor growth on III-V material
A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V...
US-9,337,280 Transistors, methods of forming transistors and display devices having transistors
A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active...
US-9,337,279 Group III-nitride-based enhancement mode transistor
A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure...
US-9,337,278 Gallium nitride on high thermal conductivity material device and method
Embodiments include but are not limited to semiconductor devices including a barrier layer, a gallium nitride channel layer having a Ga-face coupled with the...
US-9,337,277 High voltage power semiconductor device on SiC
4H SIC epiwafers with thickness of 50-100 .mu.m are grown on 4.degree. off-axis substrates. Surface morphological defect density in the range of 2-6 cm.sup.-2...
US-9,337,276 Silicon carbide semiconductor device having junction barrier Schottky diode
A silicon carbide semiconductor device includes a junction barrier Schottky diode including a substrate, a drift layer, an insulating film, a Schottky barrier...
US-9,337,275 Electrical contact for graphene part
An electrical or electronic device is disclosed. In some embodiments, an electrical device includes a single-layer graphene part extending in a lateral...
US-9,337,274 Formation of large scale single crystalline graphene
A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer...
US-9,337,273 Graphene-based semiconductor device
A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating...
US-9,337,272 Ferromagnet-free spin transistor and method for operating the same
A spin transistor includes: an input part that is made of a material exhibiting a spin Hall effect and configured to transfer electrons with a predetermined...
US-9,337,271 Silicon-carbide semiconductor device and manufacturing method therefor
It is an object of the present invention to provide a silicon carbide semiconductor device that reduces an influence of an off-angle of a silicon carbide...
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