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Patent # Description
US-9,337,168 Hermetic wafer level packaging
Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a...
US-9,337,167 Wire bonding method employing two scrub settings
A method of attaching bond wires to bond pads on an active surface of a semiconductor die, where the bond pads are disposed along four side edges of the die,...
US-9,337,166 Wire bonding apparatus and bonding method
Provided is a wire bonding apparatus capable of performing high-speed wedge wire bonding, the apparatus including: a bonding tool having a through hole and a...
US-9,337,165 Method for manufacturing a fan-out WLP with package
The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and...
US-9,337,164 Coating layer for a conductive structure
A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such...
US-9,337,163 Low profile surface mount package with isolated tab
A surface mount package includes at least one semiconductor device and a POL packaging and interconnect system formed about the at least one semiconductor...
US-9,337,162 Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
US-9,337,161 Integrated circuit package system with removable backing element having plated terminal leads and method of...
A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the...
US-9,337,160 Copper wire receiving pad
One embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection...
US-9,337,159 Semiconductor package with integrated microwave component
A semiconductor device package includes an encapsulant and a semiconductor chip. The semiconductor chip is at least partly embedded in the encapsulant. A...
US-9,337,158 Integrated circuit device and electrostatic discharge protection device thereof
An integrated circuit (IC) device includes an IC and an electrostatic discharge (ESD) protection device. The IC has a substrate, a core and a power mesh. The...
US-9,337,157 Miniature passive structures for ESD protection and input and output matching
A miniature passive structure for electrostatic discharge (ESD) protection and input/output (I/O) matching for a high frequency integrated circuit is provided....
US-9,337,156 Method for manufacturing a digital circuit and digital circuit
A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an...
US-9,337,155 Semiconductor component with moisture barrier for sealing semiconductor body
A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top...
US-9,337,154 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either...
US-9,337,153 EMI shielding and thermal dissipation for semiconductor device
A memory device including a metallic layer shielding electromagnetic radiation and/or dissipating heat, and a method of making the memory device, are disclosed....
US-9,337,152 Formulation for packaging an electronic device and assemblies made therefrom
Disclosed and claimed herein is a formulation for packaging an electronic device and assemblies made therefrom.
US-9,337,151 Semiconductor device
Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region. An interlayer insulating layer is...
US-9,337,150 Semiconductor devices including supporting patterns in gap regions between conductive patterns
An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between...
US-9,337,149 Semiconductor devices and methods of fabricating the same
Semiconductor devices may include a substrate including an active region defined by a device isolation layer, source/drain regions in the active region, word...
US-9,337,148 Chip with programmable shelf life
A structure includes a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD), a first top metal...
US-9,337,147 Semiconductor device and a method of manufacturing the same and designing the same
A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the...
US-9,337,146 Three-dimensional integrated circuit stack
A particular three-dimensional integrated circuit stack includes a first die including a first bonding interface and a first plurality of interconnect layers...
US-9,337,145 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate;...
US-9,337,144 E-fuse structure with methods of fusing the same and monitoring material leakage
The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse...
US-9,337,143 E-fuse structure with methods of fusing the same and monitoring material leakage
The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse...
US-9,337,142 Semiconductor device and manufacturing method thereof
Provided are a semiconductor device including an oscillator and a manufacturing method thereof, in which cost is low and design flexibility is high. The...
US-9,337,141 Method of forming an inductor on a semiconductor wafer
A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is...
US-9,337,140 Signal bond wire shield
A semiconductor device includes a semiconductor die having opposing first and second main surfaces, contact pads and a metal ring accessible from the first main...
US-9,337,139 Semiconductor device having compensation capacitor to stabilize power supply voltage
Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed...
US-9,337,138 Capacitors within an interposer coupled to supply and ground planes of a substrate
An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer...
US-9,337,137 Method and system for solder shielding of ball grid arrays
Methods and systems for solder shielding of ball grid arrays are disclosed and may include placing an array of solder balls onto a substrate, where the...
US-9,337,136 Method of fabricating a through-holed interposer
A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on...
US-9,337,135 Pop joint through interposer
A package includes a package component and an interposer over and bonded to the package component. The package component includes a solder region. The...
US-9,337,134 Semiconductor device
Reliability of a semiconductor device is improved. A semiconductor device has a base material comprised of insulating material having a through hole, a terminal...
US-9,337,133 Passivation scheme
An integrated circuit includes a conductive pad disposed over a substrate. A first passivation layer is disposed over the conductive pad. A second passivation...
US-9,337,132 Methods and configuration for manufacturing flip chip contact (FCC) power package
A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly...
US-9,337,131 Power semiconductor device and the preparation method
An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame...
US-9,337,130 Leadframe strip and leadframes
A leadframe strip including a first leadframe having a first die pad and a first plurality of generally parallel leads each extending outwardly relative to the...
US-9,337,129 Semiconductor device and method of manufacturing the same
A semiconductor device includes: a semiconductor element having an electrode facing a first direction; a first lead having a conductive distal end surface...
US-9,337,128 Semiconductor device
A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is...
US-9,337,127 Ultra-thin semiconductor device and preparation method thereof
A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with...
US-9,337,126 Integrated circuit and fabricating method thereof
An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first...
US-9,337,125 Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices...
Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer...
US-9,337,124 Method of integration of wafer level heat spreaders and backside interconnects on microelectronics wafers
A method for forming a wafer level heat spreader includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the...
US-9,337,123 Thermal structure for integrated circuit package
One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface...
US-9,337,122 Transferring heat through an optical layer of integrated circuitry
A computer program product or hardware description language ("HDL") design structure in a computer-aided design system for generating a functional design model...
US-9,337,121 Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet...
US-9,337,120 Multi-chip module with multiple interposers
A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to...
US-9,337,119 Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a...
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