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Patent # Description
US-9,337,118 Stress buffer structures in a mounting structure of a semiconductor device
A semiconductor device includes a bonding pad on a substrate. The semiconductor device further includes a passivation layer covering a peripheral portion of the...
US-9,337,117 Chip package and method of manufacturing the same
A package comprises a semiconductor device. The semiconductor device comprises an active surface and side surfaces. The active surface has a contact pad. The...
US-9,337,116 Semiconductor device and method of forming stepped interposer for stacking and electrically connecting...
A semiconductor substrate has a plurality of different size recesses formed in the substrate to provide a stepped interposer. A conductive via can be formed...
US-9,337,115 Chip package and method for forming the same
A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a sensing...
US-9,337,114 Ceramic board, method manufacturing thereof, image sensor package and method of manufacturing the same
Disclosed herein is a ceramic board and the manufacturing method and an image sensor package and a manufacturing method thereof, the ceramic board including a...
US-9,337,113 Semiconductor device
A semiconductor device includes a transistor, lead frames, a metal spacer, one surface of which is bonded to the transistor by a first bonding material and the...
US-9,337,112 Semiconductor device having test structure
A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active...
US-9,337,111 Apparatus and method to attach a wireless communication device into a semiconductor package
A semiconductor package includes an RFID chip positioned between a first die and a second die attached to a support substrate. The RFID chip is free of...
US-9,337,110 Semiconductor device having metal gate electrode and method of fabrication thereof
The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is...
US-9,337,109 Multi-threshold voltage FETs
A multi-threshold voltage (V.sub.t) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device...
US-9,337,108 Semiconductor device with metal gate and high-k dielectric layer, CMOS integrated circuit, and method for...
A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer,...
US-9,337,107 Semiconductor device and method for forming the same
Various embodiments provide semiconductor devices and methods for forming the same. A substrate having a dielectric layer formed thereon is provided. The...
US-9,337,106 Implant profiling with resist
A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist...
US-9,337,105 Methods for fabricating semiconductor devices with wet etching
A method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes forming transistors on a semiconductor...
US-9,337,104 Method for chemical mechanical polishing of high-K metal gate structures
A method for manufacturing a semiconductor device includes providing a substrate, a dielectric layer on the substrate, a first hard mask layer on the substrate,...
US-9,337,103 Method for removing hard mask oxide and making gate structure of semiconductor devices
A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on...
US-9,337,102 Method for manufacturing semiconductor device including doping epitaxial source drain extension regions
A method for manufacturing a semiconductor device comprises, including forming a plurality of fins on a substrate, forming, a dummy gate stack on the fins...
US-9,337,101 Methods for selectively removing a fin when forming FinFET devices
One illustrative method disclosed herein includes, among other things, forming a plurality of fins in a semiconducting substrate, each of which has a...
US-9,337,100 Apparatus and method to fabricate an electronic device
An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface....
US-9,337,099 Special constructs for continuous non-uniform active region FinFET standard cells
Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having...
US-9,337,098 Semiconductor die back layer separation method
In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape...
US-9,337,097 Chip package and method for forming the same
A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate...
US-9,337,096 Apparatus and methods for molding die on wafer interposers
Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite...
US-9,337,095 Method of manufacturing leadless integrated circuit packages having electrically routed contacts
A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts...
US-9,337,094 Method of forming contact useful in replacement metal gate processing and related semiconductor structure
A method of forming a contact is provided. The method may include forming a liner against a spacer around a gate; selectively removing an upper portion of the...
US-9,337,093 Method of manufacturing semiconductor device
The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench...
US-9,337,092 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes a groove portion formation process of forming a groove portion in a base body, a bather layer...
US-9,337,091 Semiconductor device having stable structure and method of manufacturing the same
The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured...
US-9,337,090 Semiconductor device
The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor...
US-9,337,089 Method for fabricating a semiconductor device having a bit line contact
A semiconductor device includes a semiconductor substrate having an active region defined by an isolation layer, a gate line defining a bit line contact region...
US-9,337,088 MOL resistor with metal grid heat shield
An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a...
US-9,337,087 Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same
Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the...
US-9,337,086 Die up fully molded fan-out wafer level packaging
A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front...
US-9,337,085 Air gap formation between bit lines with side protection
Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial...
US-9,337,084 Method for manufacturing contact holes of a semiconductor device
The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first...
US-9,337,083 Multi-layer metal contacts
A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least...
US-9,337,082 Metal lines having etch-bias independent height
A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level...
US-9,337,081 Semiconductor device and method of manufacturing the same
Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching...
US-9,337,080 Method for manufacturing SOI wafer
The present invention is a method for manufacturing an SOI wafer, including: implanting one or more gas ion selected from a hydrogen ion and a rare gas ion into...
US-9,337,079 Prevention of contact to substrate shorts
Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on...
US-9,337,078 Heat dissipation through device isolation
According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation...
US-9,337,077 Semiconductor device
A semiconductor device includes a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad, a first N-type diffusion region formed...
US-9,337,076 Workpiece support structure with four degree of freedom air bearing for high vacuum systems
A workpiece adjustment assembly is disclosed. The assembly can include a shaft, a spherical bearing, and a wafer support. A spherical housing receives the...
US-9,337,075 Chemical mechanical polishing fixture having lateral perforation structures
A chemical mechanical polishing fixture having lateral perforation structures includes: a holder and a retaining ring. The holder includes: an annular...
US-9,337,074 Attaching device and attaching method
An attaching device configured to attach a substrate and a support via an adhesive layer is provided with support holding members. Holding tools of the support...
US-9,337,073 3D shielding case and methods for forming the same
A package includes a die, and a molding material molding the die therein. A metal shield case includes a first metal mesh over and contacting the molding...
US-9,337,072 Apparatus and method for substrate clamping in a plasma chamber
The present invention generally provides methods and apparatus for monitoring and maintaining flatness of a substrate in a plasma reactor. Certain embodiments...
US-9,337,071 Automated wafer defect inspection system and a process of performing such inspection
An automated defect inspection system has been invented and is used on patterned wafers, whole wafers, broken wafers, partial wafers, sawn wafers such as on...
US-9,337,070 Substrate processing apparatus, substrate processing method and storage medium
A particle level varied depending on a drying processing condition can be suppressed to be stably lowered. A batch type substrate processing apparatus include a...
US-9,337,069 Method for glass sheet semiconductor coating
A system (20) and method for coating semiconductor material on glass sheets is performed by conveying the glass sheets vertically suspended at upper extremities...
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