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Patent # Description
US-9,336,114 Apparatus and method for detecting error
An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection...
US-9,336,113 Method and device for selecting a networked media device
A method and device for selecting a media device that is enabled to receive and then play or distribute digital media files, where the media device is or has...
US-9,336,112 Parallel status polling of multiple memory devices
An apparatus includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a bus that includes a plurality...
US-9,336,111 System and method for data logging within a field replaceable unit
A computer-implemented method, computer program product, and computing system for detecting the availability of status-related data within a field replaceable...
US-9,336,110 Identifying performance limiting internode data sharing on NUMA platforms
Methods, systems, and computer program products for identifying performance limiting internode data sharing on Non-Uniform Memory Access (NUMA) platforms are...
US-9,336,109 Real-time rule engine for adaptive testing of integrated circuits
A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the...
US-9,336,108 Scalable test platform
A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems...
US-9,336,107 Dynamic design partitioning for diagnosis
Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the...
US-9,336,106 Dynamically limiting bios post for effective power management
Presented herein are methods for budgeting power during a power-on self-test (POST) sequence. A determination is made for one or more stages of a...
US-9,336,105 Evaluation of multiple input signature register results
Provided is an apparatus that includes a processor comprising a plurality of processing cores and a corresponding plurality of LBIST modules, each LBIST module...
US-9,336,104 Keyboard testing machine
A keyboard testing machine for testing a keyboard of an electronic apparatus is provided. The keyboard testing machine includes a rack, a fixing base, and a...
US-9,336,103 Using a network bubble across multiple hosts on a disaster recovery site for fire drill testing of a...
A DR site is maintained containing multiple VMs distributed across multiple hosts to which a multi-tiered application can be failed over from a production site....
US-9,336,102 Systems and methods for preventing input/output performance decrease after disk failure in a distributed file...
In accordance with embodiments of the present disclosure, a method may include receiving from a plurality of data nodes of a distributed file system an...
US-9,336,101 Back-up power for a network switch
A network switch includes a power connection configured to receive power from a primary power source and at least two ports. At least a first one of the ports...
US-9,336,100 Efficient debugging of memory miscompare failures in post-silicon validation
Debugging techniques performed post-silicon, but with reference to pre-silicon phase data and/or reference model data. For example, one debugging technique is...
US-9,336,099 System and method for event-driven live migration of multi-process applications
A system, method, and computer readable medium for asynchronous live migration of applications between two or more servers. The computer readable medium...
US-9,336,098 Method of synchronizing data
A method for use in a database cluster is provided. A given transaction is executed at a first given node of the database cluster. The first given node...
US-9,336,097 Salvaging hardware transactions
A transactional memory system salvages a partially executed hardware transaction. A processor of the transactional memory system determines information about an...
US-9,336,096 Retrieval of damaged payload data on a shingled magnetic recording data carrier
A defect management system for storage devices is disclosed, which may be used in connection with shingled magnetic recording (SMR). Overlapping data tracks,...
US-9,336,095 Computing system and related data management method thereof
A method of performing data management in a computing system comprises performing a checkpointing operation comprising storing checkpoint of the computing...
US-9,336,094 Scaleout replication of an application
In one aspect, a method includes determining that a first quorum of servers is available at a production site and a target site and generating a group-set...
US-9,336,093 Information processing system and access control method
An information processing system includes a plurality of storage devices, a plurality of data access devices, and a first processor. The first processor...
US-9,336,092 Secure data deduplication
Data chunks encrypted using an encryption key are backed up to a server. Each chunk is associated with plain and encryption signatures. The plain signature is...
US-9,336,091 Reliability enhancement in a distributed storage system
Machines, systems and methods for enhancing data recovery in a data storage system, the method comprising determining whether one or more data storage mediums...
US-9,336,090 Storage apparatus comprising snapshot function, and storage control method
Storage apparatus, in response to write command specifying write destination with regards to multiple virtual areas, allocates a free real area of multiple real...
US-9,336,089 Processing apparatus, method, and non-transitory computer-readable storage medium
A processing apparatus includes a first memory, a second memory, a capacitor, and a processor coupled to the first memory and the second memory. The processor...
US-9,336,088 Method and apparatus for managing and verifying car traveling information, and system using the same
The present disclosure provides a method and apparatus for managing and verifying car traveling information, and a system using the same. The method for...
US-9,336,087 Match server for a financial exchange having fault tolerant operation
Fault tolerant operation is disclosed for a primary match server of a financial exchange using an active copy-cat instance, a.k.a. backup match server, that...
US-9,336,086 Apparatuses and methods including error correction code organization
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory...
US-9,336,085 Memory system and memory controller
A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to...
US-9,336,084 Error detection for multi-bit memory
Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of...
US-9,336,083 Apparatus and methods of programming memory cells using adjustable charge state level(s)
Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory...
US-9,336,082 Validating persistent memory content for processor main memory
Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.
US-9,336,081 Data writing and reading method, and memory controller and memory storage apparatus using the same for...
A data writing method for a rewritable non-volatile memory module is provided. The present method includes compressing an original data to generate a first data...
US-9,336,080 Transmission system and transmission method
A transmission system includes: an error correction encoding agent which converts an input data sequence into an encoded data sequence constituted of an error...
US-9,336,079 System and method for cycle slip correction
A system and method including a parity bit encoder for encoding bits of data to be transmitted with first and second parity check bits to produce successive...
US-9,336,078 Memory error detection circuitry
Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting...
US-9,336,077 Method and apparatus for decoding LDPC code
There are provided a method and apparatus for decoding an LDPC code. In this specification, a first result is calculated by performing the calculation of a...
US-9,336,076 System and method for controlling a redundancy parity encoding amount based on deduplication indications of...
According to one embodiment, a method includes determining, using a processor, which physical blocks are priority physical blocks based on at least one of: a...
US-9,336,075 Monitoring apparatus, monitoring method, and storage medium
There is provided a monitoring apparatus (1) including: an acquisition unit (10) that acquires failure information indicating that a failure has occurred in any...
US-9,336,074 Apparatus and method for detecting a fault with a clock source
A method includes receiving a first clock signal from a first clock source at a clock monitoring unit. The method also includes counting a first number of...
US-9,336,073 Write fault modulation
Systems and methods are disclosed for write fault modulation. In an embodiment, an apparatus may comprise a circuit configured to adjust a write fault value for...
US-9,336,072 Event group extensions, systems, and methods
An operating system uses non-bit aligned test masks to encode compound logical tests within the test mask. Generally, a bit within the test mask will indicate...
US-9,336,071 Administering incomplete data communications messages in a parallel computer
Administering incomplete data communications messages in a parallel computer that includes a plurality of compute nodes, with each compute node including a...
US-9,336,070 Throttling of application access to resources
A method and apparatus of a device that modifies an application sleep state of a running application is described. In an exemplary embodiment, the device...
US-9,336,069 Attributing causality to program execution capacity modifications
Techniques are described for managing program execution capacity, such as for a group of computing nodes that are provided for executing one or more programs...
US-9,336,068 Throttling of application access to resources
A method and apparatus of a device that modifies an application sleep state of a running application is described. In an exemplary embodiment, the device...
US-9,336,067 Method and system to release IMS resources used by IMS batch application programs
The embodiments provide a system for managing access to Information Management System (IMS) database resources. The system may include an initialization routine...
US-9,336,066 Hybrid linear validation algorithm for software transactional memory (STM) systems
A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring...
US-9,336,065 Semiconductor device and memory protection method
According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device...
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