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Patent # Description
US-9,344,131 Management of multiple subscriber identity modules
Management of multiple subscriber identity modules is disclosed. A method comprises: obtaining data relating to subscriber identity modules of a wireless...
US-9,344,130 Leakage calibration for a frequency converter
Techniques are described for calibration of a frequency converter for reducing a leakage-based direct current component at an output of the frequency converter....
US-9,344,129 Circuits and methods for providing a control voltage and improving switch performance in radio frequency (RF)...
An apparatus comprises at least one transmit amplifier and rectification circuitry located in the at least one transmit amplifier, which is configured to...
US-9,344,128 System and method for decoding a radio signal
A method of decoding a radio signal by an electronic device is provided. The method includes receiving the radio signal, digitizing the radio signal,...
US-9,344,127 Graphene resonator based mixer-first receiver on CMOS for digitally controlled and widely tunable RF interface
A radio frequency (RF) receiver including a baseband circuitry. The baseband circuitry can include a graphene nano-electro-mechanical (GNEMS) based system, a...
US-9,344,126 Receiving apparatus, receiving method, and program
Disclosed are a receiving apparatus, a receiving method, and a program capable of reliably obtaining predetermined information. In a case where a broadband...
US-9,344,125 Remote interference cancellation for communications systems
An interference cancellation system (ICS) may be used with a communication system to prevent or minimize interference from one or more sources. The ICS may...
US-9,344,124 Jammer resistant noise cancelling receiver front end
Techniques for providing a jammer-resistant noise-cancelling receiver front end with band-pass impedance matching and good power efficiency. In an aspect, the...
US-9,344,123 Systems and methods for historical signal interference cancellation (SIC)
Historical decoding in accordance with signal interference cancellation (SIC) or joint processing may reduce the amount of data that is re-transported across a...
US-9,344,122 Adaptive filtering for canceling distortion in radio frequency signals
Adaptive filtering is used to substantially cancel distortion in radio frequency (RF) signals. Such adaptive filtering can be used in an RF transmitting module...
US-9,344,121 Radio communication transmission system and method based on software defined radio
The disclosure discloses a Software Defined Radio (SDR)-based radio communication transmission system. A front-end analog interface unit, a Digital-to-Analog...
US-9,344,120 Adjusting redundancy in an erasure code object store to account for varying data value
Example apparatus and methods control the number of rateless erasure codes (e.g., fountain codes) stored in an object store for an item (e.g., file stored as...
US-9,344,119 Method and apparatus for transmitting and receiving R-PDCCH
A method and apparatus for transmitting and receiving a Relay Physical Downlink Control Channel (R-PDCCH) being a control channel for a relay node (RN) in a...
US-9,344,118 Apparatus and method for generating interleaver index
An apparatus for generating indexes of an interleaver for input data comprises: a main processor for calculating an index for a predetermined bit of the input...
US-9,344,117 Methods and systems for error-correction decoding
Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS...
US-9,344,116 Method for determining layer stoppage in LDPC decoding
A method for determining a layer stoppage in LDPC decoding is provided. The method may include determining the occurrence of the layer stoppage to detect and...
US-9,344,115 Method of compressing and restoring configuration data
A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data...
US-9,344,114 Compressed caching in a virtual memory system
Data compression systems, methods, and computer program products are disclosed. For each successive input word of an input stream, it is determined whether the...
US-9,344,113 Lempel Ziv compression architecture
A data compression architecture comprises a shift register structure comprising first and second parallel paths, each comprising several shift register elements...
US-9,344,112 Sampling based elimination of duplicate data
A technique for eliminating duplicate data is provided. Upon receipt of a new data set, one or more anchor points are identified within the data set. A...
US-9,344,111 N-order noise shaper
An n-order noise shaper has an order n.gtoreq.3, wherein a first set of polynomial coefficients are optimized with respect to a useful band and wherein a second...
US-9,344,110 Delta-sigma modulator and communication device
A delta-sigma modulator capable of outputting an output signal including a plurality of signals having different frequencies. The delta-sigma modulator...
US-9,344,109 Method, system and apparatus for dual mode operation of a converter
Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit...
US-9,344,108 Device having a delta-sigma modulator and a switching amplifier connected thereto
A delta-sigma modulator for a switching amplifier, which achieves a high signal-to-noise ratio (SNR) in the multi-MHz range and keeps the noise-transfer...
US-9,344,107 Continuous time ADC and filter
The invention concerns an analog to digital conversion and filtering circuit comprising: an input for receiving an analog input signal; an asynchronous...
US-9,344,106 ADC calibration
An analog-to-digital converter (ADC) includes a plurality of comparators connected to the ADC. The ADC further includes a plurality of switches, wherein...
US-9,344,105 Successive approximation analog-to-digital converter and conversion method thereof
A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter...
US-9,344,104 Digital to analog converter and analog to digital converter calibration techniques
Methods and devices for the calibration of digital to analog converters (DAC) and analog to digital converters (ADC) are disclosed. In a first step the DAC is...
US-9,344,103 High-resolution time-to-digital converter and method thereof
A circuit includes: a rectifier configured to receive a first clock signal and a second clock signal and output a rectified signal, wherein the second clock...
US-9,344,102 Threshold correction method for multi-voltage threshold sampling digitization device
A threshold correction method is for a multi-voltage threshold sampling digitization device. The method includes: generating a triangular wave, and measuring...
US-9,344,101 Semiconductor device, electronic device and sensing method
In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW3, a...
US-9,344,100 Reconfigurable local oscillator for optimal noise performance in a multi-standard transceiver
A transceiver for multi-standard operation (usable, for example, to communicate signals both of a first wireless communication standard and of a second wireless...
US-9,344,099 Continuous frequency measurement for predictive periodic synchronization
Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous...
US-9,344,098 Digital frequency-locked loop with reference clock error detection
The present disclosure is directed to a system and method for generating an output oscillating signal using an input oscillating signal that is subject to...
US-9,344,097 Fast acquisition frequency detector
A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary...
US-9,344,096 Method for detecting frequency offset of oscillator and associated circuit
A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing...
US-9,344,095 Temperature compensation for an oscillator crystal
An electronic device is equipped with an oscillator interface to be coupled to an oscillator crystal of an oscillator element. The electronic device includes an...
US-9,344,094 Temperature compensated PLL calibration
In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a...
US-9,344,093 Counter
A counter including a state determination unit and a counter reset unit is provided. The state determination unit is for receiving a current count value to...
US-9,344,092 Tunable superconducting notch filter
A technique relates to a superconductor tunable notch filter. A Josephson junction filter array is connected to a coupling pad and connected to ground. The...
US-9,344,091 Die-stacked memory device with reconfigurable logic
A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations...
US-9,344,090 Programmable logic device
An object is to provide a programmable logic device which can hold configuration data even when a power supply potential is not supplied, has short start-up...
US-9,344,089 Semiconductor integrated circuit and power-supply voltage adaptive control system
A semiconductor integrated circuit has N input terminals; N output terminals; a plurality of flip-flops (FFs) including N FFs and R redundant FFs; a selector...
US-9,344,088 Driver circuit receiving a regulated pre-driver supply voltage
A driver circuit includes first and second pluralities of series-connected inverters for pre-driving an input signal to first and second drive transistors, and...
US-9,344,087 Clock tree unit cell circuit, clock tree, and apparatus
A clock tree unit cell circuit includes a first input terminal configured to receive a clock signal from an upstream side of a clock tree; a first output...
US-9,344,086 Receiving circuits for core circuits
A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input...
US-9,344,085 Keypad with optical sensors
A keypad with optical sensors is provided. The keypad comprises keycaps, each keycap having a top surface. One or more optical sensors are located beneath top...
US-9,344,084 Touch sensor
Provided is a touch sensor having a simple structure and enabling a driver to appropriately and quickly manipulate the touch sensor as intended without looking...
US-9,344,083 Method for opening/closing of a secure hands-free access by detection of movement of a lower member of a user
A reliable and secure activation of an access based on a detection of movement in a remote access system by providing a secure method for opening/closing of an...
US-9,344,082 Rapid cutoff device and operation method for SCR DC switches
A rapid cutoff device includes a thyristor DC switch, a switch and a capacitor. An operation method includes: connecting the thyristor DC switch between a first...
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