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Method of fabrication transistor with non-uniform stress layer with stress
A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first...
High-voltage semiconductor device and method for manufacturing the same
A high-voltage semiconductor device is provided. The high-voltage semiconductor device includes a substrate; an epitaxial layer and a gate structure; a first...
MOS with recessed lightly-doped drain
LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming...
Semiconductor device and fabrication method thereof
A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode...
Vertical compound semiconductor field effect transistor on a group IV
Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor...
Semiconductor device having high-resistance conductor structure, method of
manufacturing the same and method of...
Provided is a semiconductor device including a metal oxide semiconductor transistor, a Zener diode, and a resistor. The metal oxide semiconductor transistor...
A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the...
A semiconductor device including a gate insulating film; a gate electrode; a source region of a first conductivity; a drain region of the first conductivity...
Semiconductor device having a dense trench transistor cell array
One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of...
Semiconductor device including a gate electrode on a protruding group
III-V material layer and method of...
A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate,...
Selectively area regrown III-nitride high electron mobility transistor
Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin...
Dual-gated group III-V merged transistor
There are disclosed herein various implementations of a group III-V merged cascode transistor. Such a group III-V merged cascode transistor includes a group...
Semiconductor device with self-aligned ohmic contacts
A method of fabricating a semiconductor device includes providing one or more semiconductor layers, providing a gate contact on a first surface of the one or...
Gallium nitride power devices
Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is...
Nanowire transistor devices and forming techniques
Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within...
Silicon controlled rectifier
A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a...
Vertical power component
A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity...
Methods and apparatus for ESD protection circuits
Methods and apparatus are disclosed for ESD protection circuits. An ESD protection circuit may comprise a lateral silicon controlled rectifier (SCR) circuit and...
Methods and apparatus for ESD structures
Methods and apparatus are disclosed for ESD protection circuits. An ESD protection circuit may comprise a first region of an n type material, a second region of...
Semiconductor device and manufacturing method of the same
A semiconductor device including a bipolar transistor in which a polysilicon film is used for an emitter electrode. The bipolar transistor includes a collector...
Photoresist composition, method of forming a pattern and method of
manufacturing a thin film transistor substrate
A photoresist composition, a method of forming a pattern, and a method of manufacturing a thin film transistor substrate, the composition including a solvent, a...
FinFET with embedded MOS varactor and method of making same
Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor...
Methods for manufacturing a fin structure of semiconductor device
Semiconductor devices and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacturing a semiconductor device comprises...
A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by...
Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching...
Manufacturing method of thin film transistor of display device
A manufacturing method of a thin film transistor of a display device, the method including forming a gate insulating layer on a semiconductor layer; attaching a...
Method for fabricating a recessed channel access transistor device
A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode...
Semiconductor device and method of manufacturing the same
A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration...
Electrical coupling of memory cell access devices to a word line
A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to...
Multi-finger large periphery AlInN/AlN/GaN metal-oxide-semiconductor
heterostructure field effect transistors...
MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a...
Gate contact for a semiconductor device and methods of fabrication thereof
Embodiments of a gate contact for a semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, a semiconductor device includes a...
Method for fabricating enhancement mode transistor
A method for making an enhancement-mode transistor is described. The method includes forming a first III-V compound layer on a substrate and forming a second...
Method of fabricating GaN high voltage HFET with passivation plus gate
dielectric multilayer structure
A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike,...
Transistors with a gate insulation layer having a channel depleting
A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart...
Reacted conductive gate electrodes and methods of making the same
A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material....
High voltage device with additional isolation region under gate and
manufacturing method thereof
A high voltage device includes: a substrate having a first isolation structure to define a device region; a source and a drain in the device region; a gate on...
Split gate embedded memory technology and manufacturing method thereof
A device and method of forming the device using a split gate embedded memory technology are presented. The device includes two polysilicon layers, one for...
A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer...
Semiconductor packages having a guide wall and related systems and methods
A semiconductor package includes a first package board, a first semiconductor chip arranged on the first package board, a heat transfer layer arranged on the...
Semiconductor materials, transistors including the same, and electronic
devices including transistors
According to example embodiments, a semiconductor material may include zinc, nitrogen, and fluorine. The semiconductor material may further include oxygen. The...
Direct formation of graphene on semiconductor substrates
The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming...
Semiconductor device containing graphene p-n junctions and method for
The aim of the present invention is to provide a semiconductor device containing a graphene p-n vertical tunneling-junction diode by assessing the optical and...
Field effect transistor and method for fabricating field effect transistor
A field effect transistor includes a substrate, an isolation layer, a gate, a channel, drain and a source. The substrate has an active region having a...
Method for manufacturing fin structure of finFET
The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate (200); forming a first dielectric layer...
Method of formation of germanium nanowires on bulk substrates
A material stack comprising alternating layers of a silicon etch stop material and a germanium nanowire template material is formed on a surface of a bulk...
Process of forming an electronic device having a termination region
including an insulating region
An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination...
Semiconductor device including an isolation film buried in a groove
A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer...
Deep trench isolation
An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over...
Aluminum nitride substrate and group-III nitride laminate
A substrate includes aluminum nitride, wherein the aluminum nitride substrate has on at least a surface thereof an aluminum nitride single-crystal layer having...
Etchstop layers and capacitors
Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense...