Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,343,473 Structure and method for manufacture of memory device with thin silicon body
Described herein is a structure and method of manufacturing for a memory device with a thin silicon body. The memory device may be a semiconductor comprising: a...
US-9,343,472 Memory cell with decoupled channels
A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage...
US-9,343,471 Embedded flash memory
An embedded flash memory cell and a corresponding method for fabricating the embedded flash memory cell are disclosed. In some embodiments, the flash memory...
US-9,343,470 Integration of semiconductor memory cells and logic cells
A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The...
US-9,343,469 Three dimensional NAND flash with self-aligned select gate
An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor...
US-9,343,468 Feed-forward bidirectional implanted split-gate flash memory cell
A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second...
US-9,343,467 Semiconductor device
According to this embodiment, a semiconductor device includes a semiconductor substrate, element formation regions that are formed in a line-and-space pattern...
US-9,343,466 Methods for fabricating flash memory cells and integrated circuits having flash memory cells embedded with logic
Methods for fabricating memory cells, methods for fabricating integrated circuits having memory cells, and integrated circuits having memory cells are provided....
US-9,343,465 Integrated circuit for high-voltage device protection
Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a ...
US-9,343,464 Implementing eDRAM stacked FET structure
A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are...
US-9,343,463 Method of high density memory fabrication
The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the...
US-9,343,462 Thyristor-based memory cells, devices and systems including the same and methods for forming the same
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F.sup.2, and methods for forming the same are provided....
US-9,343,461 Semiconductor device including a local wiring connecting diffusion regions
A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first...
US-9,343,460 Semiconductor device with output circuit and pad arrangements
The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is...
US-9,343,459 Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect
Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions...
US-9,343,458 Isolation structure for ESD device
Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an...
US-9,343,457 Semiconductor device
In order to provide a semiconductor device having a high ESD tolerance, a source wiring (32a) is formed on a gate (31) and a source (32) in a region of an NMOS...
US-9,343,456 Metal gate for robust ESD protection
A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a...
US-9,343,455 Apparatus and method for high voltage I/O electro-static discharge protection
An electronics chip includes a charge pump and at least one high voltage (HV) electro-static discharge (ESD) module. The charge pump is configured to provide a...
US-9,343,454 Electrostatic discharge protection structure and fabrication method thereof
An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate...
US-9,343,453 Semiconductor device
A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling...
US-9,343,452 Semiconductor devices having conductive pads and methods of fabricating the same
A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in...
US-9,343,451 Method of manufacturing semiconductor device
To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of...
US-9,343,450 Wafer scale packaging platform for transceivers
A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which...
US-9,343,449 Alternative 3D stacking scheme for DRAMs atop GPUs
Embodiments of the invention provide an integrated circuit system, which includes a first supporting substrate and a second supporting substrate, a logic chip...
US-9,343,448 Active matrix emissive micro LED display
A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and...
US-9,343,447 Optically pumped sensors or references with die-to-package cavities
An optoelectronic packaged device includes stacked components within a package including a package substrate providing side and a bottom wall. The stacked...
US-9,343,446 Diode lighting arrangement
The invention describes a diode lighting arrangement (1A,1B,1C) comprising a light-emitting diode arrangement (1,2) comprising at least two exposed serially...
US-9,343,445 Photoelectric conversion device
A photoelectric conversion device includes a circuit board, a light emitting module, a light receiving module, and an optical coupling lens. Two protrusions...
US-9,343,444 Light-emitting dies incorporating wavelength-conversion materials and related methods
In accordance with certain embodiments, electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g.,...
US-9,343,443 Light-emitting dies incorporating wavelength-conversion materials and related methods
In accordance with certain embodiments, electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g.,...
US-9,343,442 Passive devices in package-on-package structures and methods for forming the same
A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the...
US-9,343,441 Light emitter devices having improved light output and related methods
Light emitter devices having improved light output and related methods are disclosed. In one embodiment, light emitter devices can include a light emission area...
US-9,343,440 Stacked composite device including a group III-V transistor and a group IV vertical transistor
In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical...
US-9,343,439 Stack packages and methods of manufacturing the same
A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A...
US-9,343,438 Semiconductor apparatus having multiple channels
A semiconductor apparatus may include a plurality of core chips and a base chip. The plurality of core chips may respectively include a plurality of channels,...
US-9,343,437 Semiconductor package devices
Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower...
US-9,343,436 Stacked package and method of manufacturing the same
A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic...
US-9,343,435 Semiconductor device and related manufacturing method
A method for manufacturing a semiconductor device may include providing a first dielectric layer and a first set of conductive pads on a first substrate. Each...
US-9,343,434 Laser marking in packages
A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the...
US-9,343,433 Packages with stacked dies and methods of forming the same
A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first...
US-9,343,432 Semiconductor chip stack having improved encapsulation
A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip...
US-9,343,431 Dam structure for enhancing joint yield in bonding processes
A package structure includes a bottom package component, a top package component overlying and bonded to the bottom package component, and a dam between the...
US-9,343,430 Stacked wafer-level package device
Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level...
US-9,343,429 Semiconductor device and method of forming double-sided through vias in saw streets
A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the...
US-9,343,428 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the...
A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a...
US-9,343,427 Manufacturing method of semiconductor device and semiconductor device manufactured thereby
A method of manufacturing a semiconductor device that can be transferred to a circuit board with improved product reliability, and a semiconductor device...
US-9,343,426 Use of device assembly for a generalization of three-dimensional metal interconnect technologies
An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the...
US-9,343,425 Methods for bonding substrates with transient liquid phase bonds by spark plasma sintering
According to one embodiment disclosed herein, a first substrate may be bonded to a second substrate by a method which includes providing the first substrate...
US-9,343,424 Structure of circuit board with voids
A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.