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No flow underfill or wafer level underfill and solder columns
A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding...
Structure for aluminum pad metal under ball bond
A semiconductor structure is disclosed, wherein for a certain percentage of a plurality of bonding pads, the bonding pad metal may include a plurality of...
Semiconductor package and fabrication method thereof
A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive...
Universal solder joints for 3D packaging
Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving...
Bump structures for semiconductor package
A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second...
Solder bump arrangements for large area analog circuitry
An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of...
Hollow metal pillar packaging scheme
An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The...
Semiconductor device employing wafer level chip size package technology
A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the...
Copper post structure for wafer level chip scale package
In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the...
Microelectronic packages having radio frequency stand-off layers
Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of...
ESD protection for high voltage applications
An ESD module includes an ESD circuit coupled between a first source and a second source. A trigger circuit is also included in the ESD module for activating...
Method of forming MOSFET structure
A method of forming a MOSFET structure is provided. In the method, an epitaxial layer is formed. A cap layer is formed above the epitaxial layer. A first trench...
Techniques for enhancing fracture resistance of interconnects
Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via...
A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission...
Semiconductor devices having staggered air gaps
A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns...
Method to etch Cu/Ta/TaN selectively using dilute aqueous
Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper...
Method to fabricate copper wiring structures and structures formed thereby
Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high...
Device having self-repair Cu barrier for solving barrier degradation due
to Ru CMP
A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include...
Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate; a stack structure including a plurality of insulating films and a plurality of metal films disposed alternately one...
Anti-fuse of semiconductor device, semiconductor module and system each
including the semiconductor device, and...
An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar...
Stress mitigation structure for wafer warpage reduction
An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL)...
Semiconductor device having Ti- and N-containing layer, and manufacturing
method of same
A manufacturing method of a semiconductor device comprises releasing an oxidation source included in an interlayer dielectric film having an opening portion...
Semiconductor package and fabrication method thereof
A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a...
Dual damascene gap filling process
A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric...
Thick conductive stack plating process with fine critical dimension
feature size for compact passive on glass...
An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second...
BGA ballout partition techniques for simplified layout in motherboard with
multiple power supply rail
A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals...
Method of connecting a semiconductor package to a board
A method of connecting a semiconductor package to a board includes providing a board having a plurality of contact regions, providing a semiconductor package...
Semiconductor device and method of forming IPD in fan-out wafer level chip
A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive...
Semiconductor device and manufacturing method of same
To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution...
A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on...
Semiconductor substrate assembly with embedded resistance element
A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a...
Semiconductor device, manufacturing method for semiconductor device, and
There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first...
Semiconductor package and method of manufacturing the same
Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate including a mounting...
TSV formation processes using TSV-last approach
A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front...
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication...
Power semiconductor device
A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an...
Package on package structure and fabrication method thereof
A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive...
Alignment in the packaging of integrated circuits
A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package,...
Semiconductor device comprising a chip substrate, a mold, and a buffer
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a...
A semiconductor device includes a semiconductor chip comprising a first and second terminal surfaces. An insulator surrounds an outer circumference of a side...
High voltage semiconductor devices including electric arc suppression
material and methods of forming the same
A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage...
Electronic device and manufacturing method thereof
An electronic device includes a substrate; an element configured to be formed on the substrate; a sidewall member configured to enclose the element on the...
Semiconductor component with integrated crack sensor and method for
detecting a crack in a semiconductor component
A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant...
High-frequency power amplifier and method for manufacturing the same
A high-frequency power amplifier includes: a semiconductor substrate; transistor cells separated from each other and located on the semiconductor substrate; and...
Method to delineate crystal related defects
This invention generally relates to a process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of...
Optical control of multi-stage thin film solar cell production
Embodiments include methods of depositing and controlling the deposition of a film in multiple stages. The disclosed deposition and deposition control methods...
Test then destroy technique for security-focused semiconductor integrated
A method includes forming an integrated circuit device having device circuitry disposed in a device circuitry area on a substrate and a destroyable circuit...
Method of fabricating a semiconductor device
A method of fabricating a semiconductor device includes following steps. First of all, a first nanowire structure and a second nanowire structure are formed on...
Method for manufacturing a transistor in which the strain applied to the
channel is increased
Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the...
Efficient main spacer pull back process for advanced VLSI CMOS
Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si...