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Patent # Description
US-9,343,423 No flow underfill or wafer level underfill and solder columns
A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding...
US-9,343,422 Structure for aluminum pad metal under ball bond
A semiconductor structure is disclosed, wherein for a certain percentage of a plurality of bonding pads, the bonding pad metal may include a plurality of...
US-9,343,421 Semiconductor package and fabrication method thereof
A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive...
US-9,343,420 Universal solder joints for 3D packaging
Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving...
US-9,343,419 Bump structures for semiconductor package
A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second...
US-9,343,418 Solder bump arrangements for large area analog circuitry
An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of...
US-9,343,417 Hollow metal pillar packaging scheme
An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The...
US-9,343,416 Semiconductor device employing wafer level chip size package technology
A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the...
US-9,343,415 Copper post structure for wafer level chip scale package
In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the...
US-9,343,414 Microelectronic packages having radio frequency stand-off layers
Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of...
US-9,343,413 ESD protection for high voltage applications
An ESD module includes an ESD circuit coupled between a first source and a second source. A trigger circuit is also included in the ESD module for activating...
US-9,343,412 Method of forming MOSFET structure
A method of forming a MOSFET structure is provided. In the method, an epitaxial layer is formed. A cap layer is formed above the epitaxial layer. A first trench...
US-9,343,411 Techniques for enhancing fracture resistance of interconnects
Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via...
US-9,343,410 Semiconductor device
A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission...
US-9,343,409 Semiconductor devices having staggered air gaps
A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns...
US-9,343,408 Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/H.sub.2SO.sub.4 solution
Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper...
US-9,343,407 Method to fabricate copper wiring structures and structures formed thereby
Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high...
US-9,343,406 Device having self-repair Cu barrier for solving barrier degradation due to Ru CMP
A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include...
US-9,343,405 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate; a stack structure including a plurality of insulating films and a plurality of metal films disposed alternately one...
US-9,343,404 Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and...
An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar...
US-9,343,403 Stress mitigation structure for wafer warpage reduction
An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL)...
US-9,343,402 Semiconductor device having Ti- and N-containing layer, and manufacturing method of same
A manufacturing method of a semiconductor device comprises releasing an oxidation source included in an interlayer dielectric film having an opening portion...
US-9,343,401 Semiconductor package and fabrication method thereof
A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a...
US-9,343,400 Dual damascene gap filling process
A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric...
US-9,343,399 Thick conductive stack plating process with fine critical dimension feature size for compact passive on glass...
An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second...
US-9,343,398 BGA ballout partition techniques for simplified layout in motherboard with multiple power supply rail
A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals...
US-9,343,397 Method of connecting a semiconductor package to a board
A method of connecting a semiconductor package to a board includes providing a board having a plurality of contact regions, providing a semiconductor package...
US-9,343,396 Semiconductor device and method of forming IPD in fan-out wafer level chip scale package
A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive...
US-9,343,395 Semiconductor device and manufacturing method of same
To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution...
US-9,343,394 Semiconductor device
A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on...
US-9,343,393 Semiconductor substrate assembly with embedded resistance element
A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a...
US-9,343,392 Semiconductor device, manufacturing method for semiconductor device, and electronic device
There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first...
US-9,343,391 Semiconductor package and method of manufacturing the same
Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate including a mounting...
US-9,343,390 TSV formation processes using TSV-last approach
A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front...
US-9,343,389 Magnetic contacts
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication...
US-9,343,388 Power semiconductor device
A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an...
US-9,343,387 Package on package structure and fabrication method thereof
A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive...
US-9,343,386 Alignment in the packaging of integrated circuits
A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package,...
US-9,343,385 Semiconductor device comprising a chip substrate, a mold, and a buffer layer
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a...
US-9,343,384 Semiconductor device
A semiconductor device includes a semiconductor chip comprising a first and second terminal surfaces. An insulator surrounds an outer circumference of a side...
US-9,343,383 High voltage semiconductor devices including electric arc suppression material and methods of forming the same
A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage...
US-9,343,382 Electronic device and manufacturing method thereof
An electronic device includes a substrate; an element configured to be formed on the substrate; a sidewall member configured to enclose the element on the...
US-9,343,381 Semiconductor component with integrated crack sensor and method for detecting a crack in a semiconductor component
A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant...
US-9,343,380 High-frequency power amplifier and method for manufacturing the same
A high-frequency power amplifier includes: a semiconductor substrate; transistor cells separated from each other and located on the semiconductor substrate; and...
US-9,343,379 Method to delineate crystal related defects
This invention generally relates to a process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of...
US-9,343,378 Optical control of multi-stage thin film solar cell production
Embodiments include methods of depositing and controlling the deposition of a film in multiple stages. The disclosed deposition and deposition control methods...
US-9,343,377 Test then destroy technique for security-focused semiconductor integrated circuits
A method includes forming an integrated circuit device having device circuitry disposed in a device circuitry area on a substrate and a destroyable circuit...
US-9,343,376 Method of fabricating a semiconductor device
A method of fabricating a semiconductor device includes following steps. First of all, a first nanowire structure and a second nanowire structure are formed on...
US-9,343,375 Method for manufacturing a transistor in which the strain applied to the channel is increased
Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the...
US-9,343,374 Efficient main spacer pull back process for advanced VLSI CMOS technologies
Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si...
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