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Patent # Description
US-9,343,323 Method of producing aperture member
In one embodiment, an aperture member producing method includes applying a charged particle beam to a plurality of chip areas on a first substrate while...
US-9,343,322 Three dimensional stacking memory film structure
A memory device includes a plurality of stacks of alternating active strips and insulating strips. The insulating strips have effective oxide thicknesses (EOT)...
US-9,343,321 Chemical mechanical planarization using nanodiamond
A method for chemical mechanical polishing of a substrate includes polishing the substrate at a stock removal rate of greater than about 2.5 .ANG./min to...
US-9,343,320 Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench...
Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory...
US-9,343,319 Inspection method and method of manufacturing semiconductor device
First, a product to be inspected is prepared. The product to be inspected includes a substrate and a first film formed on the substrate. TDS is performed while...
US-9,343,318 Salicide formation using a cap layer
A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the...
US-9,343,317 Methods of forming silicon-containing dielectric materials and semiconductor device structures
A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals...
US-9,343,316 Methods of forming memory cells with air gaps and other low dielectric constant materials
Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a...
US-9,343,315 Method for fabricating semiconductor structure, and solid precursor delivery system
A method for fabricating a semiconductor structure is provided, including: providing a solid precursor having a first average particle size; solving the solid...
US-9,343,314 Split gate nanocrystal memory integration
A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and...
US-9,343,313 Heat treatment method and heat treatment apparatus for heating substrate by irradiating substrate with light
First irradiation which causes an emission output from a flash lamp to reach its maximum value over a time period in the range of 1 to 20 milliseconds is...
US-9,343,312 High temperature intermittent ion implantation
A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process...
US-9,343,311 Substrate treatment method
A substrate having a native oxide film formed on its surface is heated in a hydrogen atmosphere to reduce silicon dioxide to hydrogen. Additionally, silicon...
US-9,343,310 Methods of forming conductors and semiconductors on a substrate
An apparatus and a method are disclosed for forming electrical conductors and/or semiconductors on a glass substrate. The electrical conductors and/or...
US-9,343,309 Lateral oxidation process flows
Methods of laterally oxidizing features of a patterned substrate are described. A capping layer may be disposed above lateral features to laterally confine the...
US-9,343,308 Method for trimming carbon-containing film at reduced trimming rate
A method for trimming a carbon-containing film includes: (i) providing a substrate having a carbon-containing film formed thereon; (ii) supplying a trimming gas...
US-9,343,307 Laser spike annealing using fiber lasers
The disclosure is directed to laser spike annealing using fiber lasers. The method includes performing laser spike annealing of a surface of a wafer by:...
US-9,343,306 Method of fabricating thin film transistor array substrate having polysilicon with different grain sizes
A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a...
US-9,343,305 Method and device for continuously coating substrates
The invention relates to a method for the continuous coating of at least one substrate 14 with a semiconductor material e.g. CdTe. To this end a semiconductor...
US-9,343,304 Method for depositing films on semiconductor wafers
An exemplary embodiment of the present invention provides a method of depositing of a film on semiconductor wafers. In a first step, a film thickness of 3 um or...
US-9,343,303 Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor...
Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first...
US-9,343,302 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on...
US-9,343,301 Quantum dots made using phosphine
A process is disclosed for producing quantum dots (QDs) by reacting one or more core semiconductor precursors with phosphine in the presence of a molecular...
US-9,343,300 Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a...
US-9,343,299 Trench formation method for releasing a substrate from a semiconductor template
A method is provided for fabricating a semiconductor substrate by forming a porous semiconductor layer conformally on a semiconductor template and then forming...
US-9,343,298 Metal-insulator-metal capacitor and method for manufacturing thereof
The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive...
US-9,343,297 Method for forming multi-element thin film constituted by at least five elements by PEALD
A single-phase multi-element film constituted by at least four elements is formed on a substrate by plasma-enhanced atomic layer deposition (PEALD) conducting...
US-9,343,296 Apparatuses and methods for depositing SiC/SiCN films via cross-metathesis reactions with organometallic...
Disclosed herein are methods of forming SiC/SiCN film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing...
US-9,343,295 Vaporizing unit, film forming apparatus, film forming method, computer program and storage medium
A vaporizing unit, in supplying a gas material produced by vaporizing a liquid material onto a substrate to conduct a film forming process, can vaporize the...
US-9,343,294 Interconnect structure having air gap and method of forming the same
A method for forming a semiconductor device includes forming a first dielectric layer overlying a substrate, forming at least a first opening in the first...
US-9,343,293 Flowable silicon--carbon--oxygen layers for semiconductor processing
Methods are described for forming a dielectric layer on a patterned substrate. The methods may include combining a silicon-and-carbon-containing precursor and a...
US-9,343,292 Stacked semiconductor device, and method and apparatus of manufacturing the same
Provided is a method of manufacturing a stacked semiconductor device, which includes forming a stacked film on a semiconductor substrate, the stacked film...
US-9,343,291 Method for forming an interfacial layer on a semiconductor using hydrogen plasma
Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric....
US-9,343,290 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device includes forming an oxide film on a substrate by performing a cycle a predetermined number of times. The cycle...
US-9,343,289 Chemistry compatible coating material for advanced device on-wafer particle performance
To manufacture a coating for an article for a semiconductor processing chamber, the article including a body of at least one of Al, Al.sub.2O.sub.3, or SiC, and...
US-9,343,288 Semiconductor device
To increase the degree of integration of a semiconductor device such as a DCDC converter. In a semiconductor device (e.g., DCDC converter) including a...
US-9,343,287 Substrate processing apparatus including spin chuck
A substrate processing apparatus includes a plurality of chuck pins and a heat source. The chuck pin includes a conductive member made of a material containing...
US-9,343,286 Lamp with electrical components embedded in an insulation compound
A lamp (10) is described comprising a burner (14) fixed to a lamp base (12). The lamp base (12) includes a top wall oriented towards the burner (14). Within the...
US-9,343,285 Annular ion guide
An annular ion guide is disclosed comprising inner and outer electrodes. Ions are confined within an annular ion guiding region by RF or pseudo-potential...
US-9,343,284 Ion trap mass spectrometer
An electrostatic mass spectrometer and a method of mass spectrometric analysis utilizing novel traps are disclosed. The mass spectrometer includes an ion...
US-9,343,283 Internal standardization with enriched stable isotopes and cool plasma ICPMS
A method for internal standardization of cool plasma ICP-MS using one or more enriched stable isotopes includes introducing an enriched stable isotope of a...
US-9,343,282 Systems and methods for using interleaving window widths in tandem mass spectrometry
Systems and methods are provided for analyzing a sample using overlapping measured mass selection window widths. A mass range of a sample is divided into two or...
US-9,343,281 Methods and apparatus for increased ion throughput in tandem mass spectrometers
In a tandem mass spectrometry system, a first mass analyzer filters parent ions using a wide mass passband with a narrow rejection notch defined according to a...
US-9,343,280 Multi-pressure stage mass spectrometer and methods
A mass spectrometer includes a plurality of guide stages for guiding ions between an ion source and an ion detector along a guide axis. Each of the guide stages...
US-9,343,279 Data independent acquisition of product ion spectra and reference spectra library matching
Systems and methods are disclosed for identifying detectable compounds of a sample. Sample product ion spectra are received for each mass selection window of...
US-9,343,278 Data independent acquisition of product ion spectra and reference spectra library matching
Systems and methods are disclosed for quantitating detectable compounds of a sample. Sample product ion spectra are received for each mass selection window for...
US-9,343,277 Parsing events during MS.sup.3 experiments
Systems and methods are provided for reducing the time period of a CID event of an MS.sup.3 experiment and making the overall fragmentation event more generic....
US-9,343,276 Use of windowed mass spectrometry data for retention time determination or confirmation
A scan of a separating sample is received by a mass spectrometer at each interval of a plurality of intervals. The spectrometer performs at each interval one or...
US-9,343,275 Methods for characterizing carbon overcoat
A method for characterizing a carbon overcoat is provided. The method includes performing electron energy loss spectroscopy (EELS) spectrum imaging for an area...
US-9,343,274 Process kit shield for plasma enhanced processing chamber
Apparatus for processing substrates is disclosed herein. In some embodiments, an apparatus includes a first shield having a first end, a second end, and one or...
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