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Patent # Description
US-9,349,873 Oxide semiconductor device and method of fabricating the same
Provided is an oxide semiconductor device. A source, a drain, and a first gate are buried in a first dielectric layer, and the first gate is located between the...
US-9,349,871 Semiconductor device
A transistor is provided in which the bottom surface portion of an oxide semiconductor film is provided with a metal oxide film containing a constituent similar...
US-9,349,870 Method for forming low-temperature polysilicon thin film, thin film transistor and display device
A method for forming low-temperature polysilicon thin film, a thin film transistor and a display device are provided. The method for forming low-temperature...
US-9,349,869 Semiconductor device and method for manufacturing the same
To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor...
US-9,349,868 Gate all-around FinFET device and a method of manufacturing same
A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin, patterning...
US-9,349,867 Semiconductor devices and methods for manufacturing the same
Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second...
US-9,349,866 Structure and method for FinFET device
The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a fin structure disposed over a...
US-9,349,865 Method for fabricating semiconductor structures including fin structures with different strain states, and...
Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor...
US-9,349,864 Methods for selectively forming a layer of increased dopant concentration
Methods for fabricating integrated circuits including selectively forming layers of increased dopant concentration are provided. In an embodiment, a method for...
US-9,349,863 Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose...
US-9,349,862 Method of fabricating semiconductor devices
A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second...
US-9,349,861 Silicon-on-insulator substrates having selectively formed strained and relaxed device regions
A method of forming a semiconductor device substrate includes forming a donor wafer having a surface comprising regions of relaxed silicon and regions of...
US-9,349,860 Field effect transistors and methods of forming same
Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate, the substrate having a first source/drain...
US-9,349,859 Top metal pads as local interconnectors of vertical transistors
An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first...
US-9,349,858 Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device comprises a first trench formed in a substrate; a first...
US-9,349,857 Trench power MOSFET and manufacturing method thereof
A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region and a lower doped...
US-9,349,856 Semiconductor device including first interface and second interface as an upper surface of a convex protruded...
A semiconductor device includes a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer and a trench. The first...
US-9,349,855 Wide band gap semiconductor device
A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p...
US-9,349,854 Semiconductor device and method of manufacturing the same
A semiconductor device includes a vertical IGFET in a first area of a semiconductor body, the vertical IGFET having a drift zone between a body zone and a drain...
US-9,349,853 Semiconductor transistor device
According to one embodiment, a semiconductor device includes first electrode and second electrodes, first, second, third, fifth, and fourth semiconductor...
US-9,349,852 Method, structure and design structure for customizing history effects of SOI circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage...
US-9,349,851 Semiconductor device and method of forming the same
A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active...
US-9,349,850 Thermally tuning strain in semiconductor devices
A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon...
US-9,349,849 Semiconductor device and electronic device including the semiconductor device
In a semiconductor device including a transistor, an oxygen release type oxide insulating film is formed in contact with a channel formation region of the...
US-9,349,848 Gateless switch with capacitively-coupled contacts
A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the...
US-9,349,847 Semiconductor device and power converter
A semiconductor device of this invention (an IGBT with a built-in diode) includes: an n.sup.--type drift layer 1; a p-type channel region 2 that is arranged in...
US-9,349,846 Lateral bipolar junction transistors having high current-driving capability
A bipolar junction transistor includes a common base region, a plurality of emitter regions disposed in the common base region and arrayed to be spaced apart...
US-9,349,845 Self-aligned bipolar junction transistors
Device structures and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic...
US-9,349,844 Semiconductor device manufacturing method
The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a...
US-9,349,843 Method for manufacturing thin-film transistor
The present invention provides a method for manufacturing a thin-film transistor. The thin-film transistor has a bottom gate coplanar structure. The method...
US-9,349,842 Methods of forming semiconductor devices comprising ferroelectric elements and fast high-K metal gate transistors
Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the...
US-9,349,841 FinFETs and methods for forming the same
A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate...
US-9,349,840 Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second...
US-9,349,839 FinFET device structure and methods of making same
Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a...
US-9,349,838 Semiconductor structure with deep trench thermal conduction
Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal...
US-9,349,837 Recessing STI to increase Fin height in Fin-first process
A method includes forming a semiconductor fin over top surfaces of insulation regions, and forming a gate stack on a top surface and sidewalls of a middle...
US-9,349,836 Fin end spacer for preventing merger of raised active regions
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a...
US-9,349,835 Methods for replacing gate sidewall materials with a low-k spacer
A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer...
US-9,349,834 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is...
US-9,349,833 Semiconductor device and method of forming the same
A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are...
US-9,349,832 Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function...
A technique relates to forming a transistor. A dummy gate is formed on a substrate with spacers on both sides. A source and a drain are formed in the substrate,...
US-9,349,831 Integrated circuit device with well controlled surface proximity and method of manufacturing same
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a...
US-9,349,830 Semiconductor element and manufacturing method and operating method of the same
A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first...
US-9,349,829 Method of manufacturing a multi-channel HEMT
A method of manufacturing a transistor device includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron...
US-9,349,828 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride...
US-9,349,827 IGBT and diode
In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N.sup.--type drift region...
US-9,349,826 Semiconductor device and the method of manufacturing the same
A semiconductor device according to the invention includes p-type well region 3 and n.sup.+ source region 4, both formed selectively in the surface portion of...
US-9,349,825 Method for manufacturing graphene transistor based on self-aligning technology
A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene...
US-9,349,824 Oxide-nitride-oxide stack having multiple oxynitride layers
A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a...
US-9,349,823 Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and...
Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated...
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