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Patent # Description
US-9,349,772 Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM)...
A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and...
US-9,349,771 Microlens forming method and solid-state image sensor manufacturing method
A microlens forming method, comprising etching a first member and a second member arranged on the first member, the second member including a concavo-convex...
US-9,349,770 Imaging systems with infrared pixels having increased quantum efficiency
An imaging device may include an image sensor having an array of image pixels. The array of image pixels may include one or more infrared pixels that are...
US-9,349,769 Image sensor comprising reflective guide layer and method of forming the same
Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a...
US-9,349,768 CMOS image sensor with epitaxial passivation layer
The present disclosure provides a complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device. In accordance with some embodiments, the device...
US-9,349,767 Image sensors with through-oxide via structures
An imaging system may include an image sensor die stacked on top of a digital signal processor (DSP) die. The image sensor die may be a backside illuminated...
US-9,349,766 Solid-state imaging device
According to one embodiment, a solid-state imaging device includes a semiconductor layer, an organic photoelectric conversion layer, and microlenses. A...
US-9,349,765 Suspended lens system having a non-zero optical transmission substrate facing the concave surface of a...
A suspended lens system, for imaging a scene, includes (a) a single-piece lens for receiving light from the scene, wherein the single-piece lens includes a...
US-9,349,764 Embedded image sensor packages and methods of fabricating the same
An embedded image sensor package includes a core layer having a cavity therein, an image sensor chip disposed in the cavity and having a top surface on which a...
US-9,349,763 Curved image sensor systems and methods for manufacturing the same
A method for manufacturing one or more curved image sensor systems includes (a) at elevated pressure relative to atmospheric pressure, bonding a...
US-9,349,762 Pixel array, image sensor including the same, and method of compensating for local dark current
A pixel array for an image sensor is provided. The pixel array includes a dark pixel which is configured to detect a local dark current in an active pixel...
US-9,349,761 Solid-state image pickup device and color signal reading method including a plurality of electrically-coupled...
A solid-state image pickup device according to one embodiment of the present invention includes: a first substrate including first pixels arranged in a matrix;...
US-9,349,760 Method of manufacturing a TFT-LCD array substrate having light blocking layer on the surface treated...
A thin film transistor liquid crystal display (TFT-LCD) array substrate comprises a gate line, a data line, a pixel electrode and a thin film transistor. The...
US-9,349,759 Manufacturing method of low temperature poly-silicon TFT array substrate
A manufacturing method of an LTPS-TFT array substrate is provided. The exemplary method comprises a step of sequentially forming a poly-silicon layer and a...
US-9,349,758 Flexible display device with divided power lines and manufacturing method for the same
There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size...
US-9,349,757 Semiconductor device and electronic device
An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first...
US-9,349,756 Array substrate, display panel and display device
An array substrate including a plurality of pixel units each including a 2.times.2 sub-pixel area matrix, where each of the sub-pixel areas includes three...
US-9,349,755 Array substrate and display device
Disclosed is an array substrate including gate lines (210), data lines (220) formed on a base substrate and a plurality of pixel units defined by intersecting...
US-9,349,754 Display device and method for manufacturing the same
A display device including a substrate including a display area and a non-display area, wherein the non-display area comprises a gate metal line positioned on...
US-9,349,753 Array substrate, method for producing the same and display apparatus
An array substrate comprising display areas and non-display areas is provided. The non-display area comprises an area in which a plurality of gate lines and a...
US-9,349,752 Semiconductor device and manufacturing method thereof
A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment...
US-9,349,751 Semiconductor device
A semiconductor device provided with a plurality of kinds of transistors with different device structures suitable for functions of circuits is provided. The...
US-9,349,750 Semiconductor device and display device
A semiconductor device includes: a transistor including a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate...
US-9,349,749 Semiconductor device including SIU butted junction to reduce short-channel penalty
A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric...
US-9,349,748 Method for forming deep trench isolation for RF devices on SOI
A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second...
US-9,349,747 Semiconductor devices having gate stack portions that extend in a zigzag pattern
A semiconductor device includes a substrate having an upper surface extended in first and second directions perpendicular to each other, gate stack portions...
US-9,349,746 Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices
Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and...
US-9,349,745 3D NAND nonvolatile memory with staggered vertical gates
A memory device includes a plurality of stacks of conductive strips, a plurality of word lines over and orthogonal to the plurality of stacks of conductive...
US-9,349,744 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first channel layer, a second channel layer protruding from the first channel layer, a pipe gate including a silicide area...
US-9,349,743 Method of manufacturing semiconductor device
To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a...
US-9,349,742 Embedded memory and methods of forming the same
An embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate. The first source and drain regions are on...
US-9,349,741 Recessed salicide structure to integrate a flash memory device with a high .kappa., metal gate logic device
An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the...
US-9,349,740 Non-volatile storage element with suspended charge storage region
Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices....
US-9,349,739 OTP memory
The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and...
US-9,349,738 Content addressable memory (CAM) device having substrate array line structure
A content addressable memory (CAM) device can include a plurality of CAM cells each formed within a cell area of a substrate. Each cell area can have a cell...
US-9,349,737 Passing access line structure in a memory device
A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The...
US-9,349,736 Method for manufacturing high-strength structural stacked capacitor
The instant disclosure relates to a method for manufacturing high-strength structural stacked capacitor. The novel feature of the instant disclosure is forming...
US-9,349,735 Semiconductor device
An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when...
US-9,349,734 Selective FuSi gate formation in gate first CMOS technologies
The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully...
US-9,349,733 Gate structure having spacer with flat top surface and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first gate structure formed over a substrate....
US-9,349,732 High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep...
Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide...
US-9,349,731 Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern...
US-9,349,730 Fin transformation process and isolation structures facilitating different Fin isolation schemes
Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for...
US-9,349,729 Semiconductor structures and fabrication method thereof
A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region; and forming a first...
US-9,349,728 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal-oxide semiconductor (MOS)...
US-9,349,727 Semiconductor device
In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions...
US-9,349,726 Semiconductor device fabrication method and structure
A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain...
US-9,349,725 Stripe orientation for trenches and contact windows
A semiconductor device includes a semiconductor layer having first and second main surfaces, with the first surface defining a plane containing first and second...
US-9,349,724 Semiconductor device having capacitors
A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node...
US-9,349,723 Semiconductor device and method of forming passive devices
A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a...
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