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| Patent # | Description |
|---|---|
| US-9,349,722 |
Semiconductor memory device including a memory cell comprising a D/A
converter A nonvolatile semiconductor device is provided. Each memory cell in a semiconductor device includes a D/A converter and an amplifier transistor. An output... |
| US-9,349,721 |
Semiconductor device A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor... |
| US-9,349,720 |
Integrated circuit device An integrated circuit device includes a semiconductor substrate, an active element and a passive element. The active element is made of the semiconductor... |
| US-9,349,719 |
Semiconductor device A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second... |
| US-9,349,718 |
ESD snapback based clamp for finFET There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a... |
| US-9,349,717 |
Noise cancellation for a magnetically coupled communication link utilizing
a lead frame An integrated circuit package includes an encapsulation and a lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame... |
| US-9,349,716 |
Electrostatic discharge protection device An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a... |
| US-9,349,715 |
Depletion mode group III-V transistor with high voltage group IV enable
switch There are disclosed herein various implementations of a half-bridge or multiple half-bridge switch configurations used in a voltage converter circuit using at... |
| US-9,349,714 |
Method of manufacturing semiconductor device, block stacked body, and
sequential stacked body A method of manufacturing a semiconductor device is provided which is capable of improving productivity and reliability. The method of manufacturing a... |
| US-9,349,713 |
Semiconductor package stack structure having interposer substrate Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate... |
| US-9,349,712 |
Doubled substrate multi-junction light emitting diode array structure The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal... |
| US-9,349,711 |
Semiconductor device with face-to-face chips on interposer and method of
manufacturing the same A method of making a semiconductor device with face-to-face chips on interposer includes the step of attaching a chip-on-interposer subassembly on a heat... |
| US-9,349,710 |
Chip package and method for forming the same A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second... |
| US-9,349,709 |
Electronic component with sheet-like redistribution structure An electronic component comprising an electrically conductive chip carrier comprising an electrically insulating core structure at least partially covered with... |
| US-9,349,708 |
Chip stacked package structure and electronic device A chip stacked package structure includes a first chip and a second chip, where the second chip is stacked with the first chip and the second chip includes a... |
| US-9,349,707 |
Contact arrangements for stackable microelectronic package structures with
multiple ranks An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact... |
| US-9,349,706 |
Method for package-on-package assembly with wire bonds to encapsulation
surface A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface... |
| US-9,349,705 |
Method of fabricating a semiconductor structure having conductive bumps
with a plurality of metal layers A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer... |
| US-9,349,704 |
Jointed structure and method of manufacturing same A jointed structure comprises a first metal layer and a second metal layer. The first metal layer and the second metal layer are jointed together and have... |
| US-9,349,703 |
Method for making high density substrate interconnect using inkjet
printing Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a... |
| US-9,349,702 |
Chip bonding method and driving chip of display A chip bonding method for bonding a chip on a display panel is provided. The chip includes a joint face, a rear face, input bumps and output bumps. The joint... |
| US-9,349,701 |
Self-aligning conductive bump structure and method of fabrication A semiconductor device includes a substrate having a major surface and conductive bumps distributed over the major surface of the substrate. Each conductive... |
| US-9,349,700 |
Semiconductor device and method of forming stress-reduced conductive joint
structures A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second... |
| US-9,349,699 |
Front side copper post joint structure for temporary bond in TSV
application A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon. A... |
| US-9,349,698 |
Integrated WLUF and SOD process This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the... |
| US-9,349,697 |
Microbump and sacrificial pad pattern Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is... |
| US-9,349,696 |
Integrated antennas in wafer level package A semiconductor module comprises a wafer package comprising an integrated circuit (IC) device embedded within the wafer package and a layer comprising at least... |
| US-9,349,695 |
Semiconductor integrated device including FinFET device and protecting
structure A semiconductor integrated device includes a substrate having an active region defined thereon, a plurality of active fins positioned in the active region, and... |
| US-9,349,694 |
Method of manufacturing a semiconductor device According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The ... |
| US-9,349,693 |
Semiconductor device with an isolation structure coupled to a cover of the
semiconductor device A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is... |
| US-9,349,692 |
Integrated voltage regulator with embedded passive device(s) for a stacked
IC A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An... |
| US-9,349,691 |
Semiconductor device with reduced via resistance A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at... |
| US-9,349,690 |
Semiconductor arrangement and formation thereof A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal... |
| US-9,349,689 |
Semiconductor devices including conductive features with capping layers
and methods of forming the same Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an... |
| US-9,349,688 |
Systems and methods to enhance passivation integrity A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is... |
| US-9,349,687 |
Advanced manganese/manganese nitride cap/etch mask for air gap formation
scheme in nanocopper low-K interconnect After forming a manganese (Mn)-containing cap layer over interconnects embedded in an interlevel dielectric (ILD) layer, a lithographic stack is formed over the... |
| US-9,349,686 |
Reduced height M1 metal lines for local on-chip routing Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path... |
| US-9,349,685 |
Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second... |
| US-9,349,684 |
Semiconductor package and electronic apparatus including the same Provided are a curved semiconductor package, and a device including the semiconductor package. The semiconductor package includes: a flexible printed circuit... |
| US-9,349,683 |
Chip-on-film package having bending part A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed... |
| US-9,349,682 |
Semiconductor chip and semiconductor chip package each having signal paths
that balance clock skews A semiconductor chip is provided. The semiconductor chip includes a first circuit, a second circuit, a third circuit, a first signal path and a second signal... |
| US-9,349,681 |
Semiconductor device package and manufacturing method thereof Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of... |
| US-9,349,680 |
Chip arrangement and method of manufacturing the same A chip arrangement is provided which comprises a carrier; and at least two chips arranged over the carrier; wherein a continuous insulating layer is arranged... |
| US-9,349,679 |
Singulation method for semiconductor package with plating on side of
connectors A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein... |
| US-9,349,678 |
Chip having a pillar electrode offset from the bonding pad The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a... |
| US-9,349,677 |
Stacked half-bridge package with a common leadframe According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input,... |
| US-9,349,676 |
Chip rotated at an angle mounted on die pad region A package includes: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package; a die pad region surrounded... |
| US-9,349,675 |
Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes preparing a lead frame provided with a die pad having an upper surface and a plurality of leads being... |
| US-9,349,674 |
Wiring board unit, manufacturing method thereof, and manufacturing method
of wiring board with lead A wiring board unit includes: a polygonal wiring board having three or more sides in top view, a product insulating part comprising a plurality of external... |
| US-9,349,673 |
Substrate, method of manufacturing substrate, semiconductor device, and
electronic apparatus A substrate includes a first insulating layer provided on a base board, a second insulating layer provided on the first insulating layer, a third insulating... |
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