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Patent # Description
US-9,349,672 Microelectronic package
A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one...
US-9,349,671 Integrated circuit chip comprising electronic device and electronic system
An electronic device includes a substrate wafer made of many layers of an insulating material and including an electrical connection network. An integrated...
US-9,349,670 Semiconductor die assemblies with heat sink and associated systems and methods
Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a...
US-9,349,669 Reduced stress TSV and interposer structures
A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive...
US-9,349,668 Semiconductor device
A semiconductor device includes; a semiconductor layer mainly made of GaN; a protective film provided to have electrical insulation property and configured to...
US-9,349,667 Method of manufacturing stacked package
A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a...
US-9,349,666 Integrated circuit packaging system with package stacking
An integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact...
US-9,349,665 Methods and apparatus of packaging of semiconductor devices
Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal...
US-9,349,664 Method for manufacturing light emitting device and light emitting device
A manufacturing method of a light emitting device includes a light emitting element disposed over a substrate and a reflective resin disposed along the side...
US-9,349,663 Package-on-package structure having polymer-based material for warpage control
A package on package structure providing mechanical strength and warpage control includes a first package component, a second package component, and a first set...
US-9,349,662 Test structure placement on a semiconductor wafer
A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor...
US-9,349,661 Wafer thinning endpoint detection for TSV technology
Embodiments of the present invention provide an apparatus and method for wafer thinning endpoint detection. Embodiments of the present invention utilize through...
US-9,349,660 Integrated circuit manufacturing tool condition monitoring system and method
A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an...
US-9,349,659 Methods for probing semiconductor fins and determining carrier concentrations therein
A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at...
US-9,349,658 Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of...
One illustrative embodiment involves forming a plurality of trenches in a substrate so as to define a fin, forming a first oxidation-blocking layer of...
US-9,349,657 Fabrication methods of integrated semiconductor structure
A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer...
US-9,349,656 Method of forming a complementary metal-oxide-semiconductor (CMOS) device
A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS...
US-9,349,655 Method for mechanical stress enhancement in semiconductor devices
The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one...
US-9,349,654 Isolation for embedded devices
Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first,...
US-9,349,653 Manufacturing method of semiconductor structure for preventing surface of fin structure from damage and...
A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure...
US-9,349,652 Method of forming semiconductor device with different threshold voltages
A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature,...
US-9,349,651 Semiconductor device and method for fabricating the same
Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe...
US-9,349,650 Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs
A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A...
US-9,349,649 Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs
A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A...
US-9,349,648 Hybrid wafer dicing approach using a rectangular shaped two-dimensional top hat laser beam profile or a linear...
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
US-9,349,647 Cutting method
A cutting method for cutting by a cutting blade a workpiece which includes metal at least in a predetermined cutting position. The cutting method includes a...
US-9,349,646 Wafer processing method including a filament forming step and an etching step
A wafer processing method for dividing a wafer along a plurality of division lines to obtain a plurality of individual chips. The wafer processing method...
US-9,349,645 Apparatus, device and method for wafer dicing
An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die...
US-9,349,644 Semiconductor device producing method
In a method for producing a semiconductor device having a through electrode structure, a masking material is formed so as to bridge over a through hole formed...
US-9,349,643 Apparatus and method for thin wafer transfer
A wafer transfer assembly and method of using the assembly to transfer device wafers between processing tools in a manufacturing process are described herein....
US-9,349,642 Method of forming contact layer
A method of forming a contact layer on a substrate having a contact hole to make a contact between the substrate and a buried metal material, includes disposing...
US-9,349,641 Wafer with improved plating current distribution
A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of...
US-9,349,640 Electrode pair fabrication using directed self assembly of diblock copolymers
Structures including alternating first U-shaped electrodes and second U-shaped electrodes and contact pads interconnecting the first and the second U-shaped...
US-9,349,639 Method for manufacturing a contact structure used to electrically connect a semiconductor device
A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon,...
US-9,349,638 Memory device
A memory device according to embodiments includes a cell array region. The cell array region comprises a plurality of transistors sharing a word line, a...
US-9,349,637 Method for void-free cobalt gap fill
Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt,...
US-9,349,636 Interconnect wires including relatively low resistivity cores
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes...
US-9,349,635 Integrated circuits and methods of forming the same with multi-level electrical connection
Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that...
US-9,349,634 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active...
US-9,349,633 Semiconductor devices and methods of manufacturing the same
A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating...
US-9,349,632 Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such...
US-9,349,631 Method for defining an isolation region(s) of a semiconductor structure
Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with...
US-9,349,630 Methods and apparatus for electrostatic chuck repair and refurbishment
In one embodiment of the invention, a substrate support assembly comprises an electrostatic chuck having an electrode embedded therein and having an aperture...
US-9,349,629 Touch auto-calibration of process modules
Methods and systems for the touch auto-calibration for robot placement of substrate in process modules are provided. Touch auto-calibration allows for the...
US-9,349,628 Method and an alignment plate for engaging a stiffener frame and a circuit board
Methods and apparatus for coupling a stiffener frame to a circuit board are disclosed. In one aspect, a method for engaging a stiffener frame and a circuit...
US-9,349,627 Lid opening/closing system for closed container and substrate processing method using same
Adjacent to an opening portion in an FISM system is provided an enclosure that encloses the operation space of a door and has a second opening portion opposed...
US-9,349,626 Buffer units, substrate processing apparatuses, and substrate processing methods
Provided is a buffer unit, which includes a frame including a base plate, a first vertical plate, and a second vertical plate, wherein the first and second...
US-9,349,625 Substrate conveyance method and substrate processing apparatus
Provided is a substrate conveyance method where a segment which can simultaneously hold M pieces of substrates defined by an integer M of 2 or more is provided,...
US-9,349,624 Semiconductor wafer monitoring apparatus and method
Metrology methods and apparatus for semiconductor wafer fabrication in which data for metrology is obtained by detecting a measurable property of a monitored...
US-9,349,623 Fine temperature controllable wafer heating system
Disclosed are a method and a system for processing wafers in fabricating a semiconductor device where disposing chemicals and wafer heating are needed for...
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