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Patent # Description
US-9,349,470 Memory read apparatus and methods
Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential,...
US-9,349,469 Program verify with multiple sensing
A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After...
US-9,349,468 Operational amplifier methods for charging of sense amplifier internal nodes
Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the...
US-9,349,467 Read threshold estimation in analog memory cells using simultaneous multi-voltage sense
A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single...
US-9,349,466 Nonvolatile memory device having selectable sensing modes, memory system having the same and programming method...
A non-volatile memory device includes a sensing mode selector configured to select a sensing mode according to environment information. A page buffer senses a...
US-9,349,465 Semiconductor memory device and method of operating the same
A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The...
US-9,349,464 Non-volatile semiconductor device
A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word...
US-9,349,463 Semiconductor device and method of manufacturing the same
To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper...
US-9,349,462 Flash memory and programming method thereof
A programming method of an NAND flash memory is provided, for narrowing a distribution width of a threshold voltage. The method includes a step of verification...
US-9,349,461 Applying substantially the same voltage differences across memory cells at different locations along an access...
An embodiment of a method of programming might include applying a first voltage difference across a first memory cell to be programmed, where applying the first...
US-9,349,460 Semiconductor memory device and data write method thereof
A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest...
US-9,349,459 Programming memory cells using smaller step voltages for higher program levels
Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first...
US-9,349,458 Biasing of unselected blocks of non-volatile memory to reduce loading
Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND...
US-9,349,457 High voltage switch, nonvolatile memory device comprising same, and related method of operation
A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch...
US-9,349,456 Method of operating non-volatile memory device
A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to...
US-9,349,455 Nonvolatile memory devices and driving methods thereof
Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected...
US-9,349,454 Semiconductor device and electronic device
A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The...
US-9,349,453 Semiconductor memory cell and driver circuitry with gate oxide formed simultaneously
The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in...
US-9,349,452 Hybrid non-volatile memory cells for shared bit line
A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data...
US-9,349,451 Resistive memory and repairing method thereof
A resistive memory and a repairing method of the resistive memory are provided. Steps of the repairing method includes: operating a plurality of set-reset...
US-9,349,450 Memory devices and memory operational methods including single erase operation of conductive bridge memory cells
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with...
US-9,349,449 Resistance change type memory
A resistance change type memory includes a memory cell including a first resistance change element as a memory element; a reference cell including a second...
US-9,349,448 Operating a resistive array
The present invention is a means and method for constructing and operating a 3-D array and, more particularly, a 3-D memory array. This array can be...
US-9,349,447 Controlling coupling in large cross-point memory arrays
In various embodiments, quench switches are utilized within a cross-point memory array to minimize parasitic coupling in lines proximate selected lines.
US-9,349,446 Semiconductor memory device and method of controlling the same
A plurality of word lines extend in a first direction and are disposed in a second direction and a third direction. A plurality of bit lines extend in the third...
US-9,349,445 Select devices for memory cell applications
Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more non-ohmic select devices can...
US-9,349,444 Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based...
Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied...
US-9,349,443 Method and system for programming multi-level cell memory
A method and a system for programming a multi-level cell (MLC) memory are provided. A first count is 1 initially. The method comprises the following steps. A...
US-9,349,442 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit...
US-9,349,441 Fractional bits in memory cells
Methods, devices, modules, and systems for programming memory cells are disclosed. One method embodiment includes storing charges corresponding to a data state...
US-9,349,440 Non-volatile SRAM with multiple storage states
Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. The multi-storage state...
US-9,349,439 Semiconductor device
An intermediate mode is set between the active mode in which a threshold voltage is low and a standby mode in which a threshold voltage is high. When a mode is...
US-9,349,438 Semiconductor storage device
A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural...
US-9,349,437 Memory cell having built-in read and write assist
A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching...
US-9,349,436 Semiconductor memory and method of making the same
A semiconductor cell comprises a plurality of metal layers. A first layer comprises a VDD conductor, a bit-line, and a complimentary bit-line. Each of the VDD...
US-9,349,435 Memory device and semiconductor device
Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and...
US-9,349,434 Variable strobe for alignment of partially invisible data signals
A method of sampling data signals in response to a timing signal includes receiving data signals that are skewed relative to each other. Each data signal has a...
US-9,349,433 Hidden refresh of weak memory storage cells in semiconductor memory
In an example, the present invention provides a computing system. The system has a memory interface device comprising a counter, a dynamic random access memory...
US-9,349,432 Reference voltage modification in a memory device
A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory...
US-9,349,431 Systems and methods to refresh storage elements
A method of performing refresh operations on a storage device includes identifying word lines coupled to weak storage elements. The method also includes...
US-9,349,430 Memory device and memory system including the same
A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory...
US-9,349,429 Field programming method for magnetic memory devices
There is provided a method for operating a magnetic memory device. The method comprises selecting a subset of magnetic memory cells of the magnetic memory...
US-9,349,428 Sense amplifier, nonvolatile memory device including the sense amplifier and sensing method of the sense amplifier
A sense amplifier, a nonvolatile memory device including the sense amplifier and a sensing method of the sense amplifier are provided. The sense amplifier...
US-9,349,427 Method for screening arrays of magnetic memories
A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in...
US-9,349,426 Non-volatile random access memory (NVRAM)
A non-volatile memory device includes an array of non-volatile (NV) memory cells organized in pairs. Each pair is included with a transistor to form a memory...
US-9,349,425 Semiconductor device for driving word line
A semiconductor device includes a driving signal generation unit configured to selectively drive a sub word line driving signal in response to a sub word line...
US-9,349,424 Semiconductor apparatus configured to manage an operation timing margin
A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one...
US-9,349,423 Single node power management for multiple memory devices
Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on...
US-9,349,422 Supporting calibration for sub-rate operation in clocked memory systems
The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate...
US-9,349,421 Memory interface
A data path interface for transferring data to a memory device, comprising: programmable delay units ("PDUs"), wherein data is received by the interface...
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