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Patent # Description
US-9,356,628 Dynamically reconfiguring rebuild agents for erasure code rebuild
Example apparatus and methods support reconstructing an item from a set of erasure codes (e.g., fountain codes). Information about computer resources available...
US-9,356,627 Method and apparatus for improving transmission of data on a bandwidth mismatched channel
A method and apparatus for providing transmission on a channel in a network are disclosed. For example, the method receives a plurality of source samples,...
US-9,356,626 Data encoding for data storage system based on generalized concatenated codes
Data is obtained at a data storage system. Codewords are generated from the obtained data. The codewords are computed using a generalized concatenated code and...
US-9,356,625 Frame generation method, optical transmission device, and optical transmission system
A frame generation method in an optical transmission system that transmits a transmission frame including a payload area for storing therein information data...
US-9,356,624 Encoding method, and decoding method
An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The...
US-9,356,623 LDPC decoder variable node units having fewer adder stages
In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and...
US-9,356,622 Apparatus and method for reconstructing a bit sequence with preliminary correction
A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially...
US-9,356,621 Hierarchical data compression and computation
According to embodiments of the present invention, machines, systems, methods and computer program products for hierarchical compression of data are presented...
US-9,356,620 Method for producing video coding and programme-product
According to the invention, there are provided sets of contexts specifically adapted to encode special coefficients of a prediction error matrix, on the basis...
US-9,356,618 Second order loop filter and multi-order delta sigma modulator including the same
Provided is a second order loop filter (LF). The second order LF includes: an operational amplifier including a first input, a second input receiving a...
US-9,356,617 Uniform distribution dithering in sigma-delta A/D converters
Apparatus and methods for analog-to-digital converters are provided. In an example, a sigma-delta analog-to-digital converter (ADC) can include a modulator...
US-9,356,616 Pipelined interpolating sub-ranging SAR analog-to-digital converter
A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled...
US-9,356,615 Systems and methods for comparator calibration
The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator...
US-9,356,614 Thermometer code converter
A code converter is provided. The code converter includes a plurality of serial shift registers arranged to convert an input to a thermometer output. The code...
US-9,356,613 Pulse density modulation digital-to-analog converter with triangle wave generation
A phase accumulator style circuit generates an output stream of pulses. The density of the pulse stream is proportional to the input data value relative to the...
US-9,356,612 Method and apparatus to calibrate frequency synthesizer
Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal...
US-9,356,611 Systems and methods involving phase detection with adaptive locking/detection features
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a...
US-9,356,610 Clock data recovery circuit and semiconductor device
A clock data recovery circuit is configured to receive an input data signal formed of a series of input data pieces synchronized with a reference clock signal,...
US-9,356,609 Phase switching PLL and calibration method
The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output...
US-9,356,608 Method and apparatus for controlling mismatch in a voltage controlled oscillator array
A method and system are provided for reducing mismatch between oscillators in an LC VCO array. In an implementation, a method comprises measuring the mismatch...
US-9,356,607 Controller unit and device for resetting an oscillator excited by a harmonic oscillation, and yaw rate sensor
A controller unit includes a PI-controller for harmonic command variables. The transfer function of the PI-controller has a conjugate complex pole at a...
US-9,356,606 Clock generator using free-running oscillator and method therefor
A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator...
US-9,356,605 Period measuring circuit and semiconductor device including the same
A semiconductor device includes: a counting detection block suitable for generating a counting value of a clock signal transmitted through a first transmission...
US-9,356,604 Integrated circuit and method for manufacturing the same
An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The...
US-9,356,603 Thermally tempered glass substrate using CTE mismatched layers and paste mixtures for transient electronic systems
A thermally tempered glass substrate for transient electronic systems (i.e., including electronic devices that visually disappear when triggered to do so)...
US-9,356,602 Management of memory resources in a programmable integrated circuit
An approach for management of memory in a programmable integrated circuit (IC) includes configuring a memory map of the programmable IC with an association of a...
US-9,356,601 Programmable logic device
A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the...
US-9,356,600 IO driver impedance calibration
An IO driver for an integrated circuit and a method for calibrating such an IO driver are provided. The IO driver comprises a plurality of IO driver cells, a...
US-9,356,599 Differential driver circuit having bias equalizing pre-drivers
A differential driver circuit includes a differential driver configured to drive an output signal based upon a positive leg pull up signal, a positive leg pull...
US-9,356,598 Threshold logic gates with resistive networks
This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate...
US-9,356,597 Bidirectional data exchange circuit
A bidirectional data exchange circuit (10) includes a buffer (16) having paired terminals (A1 . . . A8, B1 . . . B8), a transfer direction input (20), an input...
US-9,356,596 Driving circuit and driving method
The present technology relates to a driving circuit and a driving method, in which power loss at the time of switching an FET (Field Effect Transistor) can be...
US-9,356,595 Bidirectional two-base bipolar junction transistor devices, operation, circuits, and systems with...
Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching....
US-9,356,594 Switched-mode power supply using variable bias current
There is provided a switched-mode power supply including: a PWM control unit generating a clock signal having pulse widths of the clock depending on a load to...
US-9,356,593 Distributed virtual-ground switching for SAR and pipelined ADC
Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs...
US-9,356,592 Method of reducing current collapse of power device
According to example embodiments, a method of operating a power device includes applying a control voltage to a control electrode of the power device, where the...
US-9,356,591 Crosspoint switch with separate voltage sources for input and output ports
A crosspoint switch device has a plurality of input ports each connected to a respective voltage source and a plurality of output ports each connected to a...
US-9,356,590 Production test trimming acceleration
Systems and methods for production test trimming acceleration. In an illustrative, non-limiting embodiment, a method may include providing a first trim code to...
US-9,356,589 Interchannel skew adjustment circuit
An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit...
US-9,356,588 Linearity of phase interpolators using capacitive elements
A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each...
US-9,356,587 High voltage comparison circuit
A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first...
US-9,356,586 Circuit and method to extend a signal comparison voltage range
A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is...
US-9,356,585 Image pickup device
An electronic device according to one or more embodiments of the present invention comprises an output line, a current mirror circuit and a comparator. Current...
US-9,356,584 Level shifter
A level shifter for high-speed level shifting includes a first P-channel transistor, comprising a gate coupled to a drain, and a source coupled to a system...
US-9,356,583 Flip-flop circuit
A flip-flop circuit includes a first latch, a trigger stage and a second latch. The first latch is configured to latch a selected signal in response to a first...
US-9,356,582 Low jitter tunable voltage control oscillator with self calibration circuits to reduce chip fabrication process...
A voltage controlled oscillator (VCO) which can be configured with a smaller tuning range than is ordinarily required is presented. Ordinarily, the tuning range...
US-9,356,581 Data output circuit of a semiconductor apparatus
A data output circuit of a semiconductor apparatus is provided. The data output circuit may include a pull-up driver including a plurality of leg units...
US-9,356,580 Insulated gate semiconductor element drive device
A drive circuit includes a constant current circuit which supplies a constant current to the gate of an IGBT and on-operates the IGBT; a discharge circuit which...
US-9,356,579 Waveform generation
A predetermined waveform is generated using a lower frequency clock signal (16) and a higher frequency clock signal (18). The waveform transitions between first...
US-9,356,578 Spurious frequency attenuation servo without tuning filter
A spurious frequency attenuation servo comprises a first signal generated at a first frequency including at least one spur at at least one respective spurious...
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