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Patent # Description
US-9,356,176 Inverted metamorphic multijunction solar cell with metamorphic layers
A multijunction solar cell having at least four solar subcells includes a first solar subcell having a first band gap. A first graded interlayer adjacent to the...
US-9,356,175 Photovoltaic module, method for electrically connecting a plurality of photovoltaic cells, and device for...
In various embodiments, a photovoltaic module may include: a plurality of photovoltaic cells, at least one photovoltaic cell of the number of photovoltaic cells...
US-9,356,174 Roofing flashings and roofing systems and photovoltaic roofing systems using the same
The present invention relates more particularly to improved flashings for use in integrating specialized roof-mounted structures, such as photovoltaic devices...
US-9,356,173 Dynamically reconfigurable photovoltaic system
A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array...
US-9,356,172 Solar cell and method for manufacturing same
Disclosed is a solar cell including a support substrate, a barrier layer on the support substrate, and a photo-electro conversion part on the barrier layer. The...
US-9,356,171 Method of forming single-crystal semiconductor layers and photovaltaic cell thereon
A method for forming single crystal or large-crystal-grain thin-film layers deposits a thin-film amorphous, nanocrystalline, microcrystalline, or...
US-9,356,170 THz distributed detectors and arrays
Terahertz (THz) distributed detectors, and arrays of detectors that utilize structured surface plasmonic effects for more efficient coupling to free space are...
US-9,356,169 Apparatus, system and method of back side illumination (BSI) complementary metal-oxide-semiconductor (CMOS)...
Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For...
US-9,356,168 Method of manufacturing CI(G)S nano particles for manufacturing light absorption layer and CI(G)S nano...
Disclosed are a method of preparing CI(G)S nano particles forming a light absorption layer of solar cells, including dissolving at least one Group VI source...
US-9,356,167 Semiconductor ultraviolet (UV) photo-detecting device
An ultraviolet (UV) photo-detecting device, including: a first nitride layer; a secondary light absorption layer disposed on the first nitride layer; a primary...
US-9,356,166 Cooled optical light guide for low-level light detectors and method of temperature stabilization for imaging...
A cooled optical light guide is provided having a conduit having a translucent top and a translucent bottom wherein at least a portion of the translucent top of...
US-9,356,165 Semiconductor device and method for manufacturing the same
A semiconductor device includes a substrate and a first insulating layer. The first insulating layer includes a first lower layer and a first upper layer on the...
US-9,356,164 Integrated photodetector waveguide structure with alignment tolerance
An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a...
US-9,356,163 Structure and method of integrating waveguides, photodetectors and logic devices
A method for monolithically integrating semiconductor waveguides, photodetectors and logic devices, i.e., field effect transistors, on a same substrate is...
US-9,356,162 High efficiency group III-V compound semiconductor solar cell with oxidized window layer
The present application utilizes an oxidation process to fabricating a Group III-V compound semiconductor solar cell device. By the oxidation process, a window...
US-9,356,161 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes: a photoelectric conversion section made of semiconductor; a color filter made of an inorganic material to which a metal ion is...
US-9,356,160 Flat panel sensor and flat panel detector
A flat panel sensor and a flat panel detector are provided on the basis of a top-gate TFT structure. The flat panel sensor comprises a base substrate, and a...
US-9,356,159 Three-dimensional semiconductor memory devices
Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common...
US-9,356,158 Electronic device including a tunnel structure
An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the...
US-9,356,157 Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices
Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an...
US-9,356,156 Stable high mobility MOTFT and fabrication at low temperature
A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer...
US-9,356,155 Semiconductor device structures and arrays of vertical transistor devices
A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region...
US-9,356,153 Thin film transistor, display panel having the same and method of manufacturing the same
A thin film transistor includes a bottom gate electrode, a top gate electrode and an active pattern. The top gate electrode includes a transparent conductive...
US-9,356,152 Semiconductor device, electronic device, and method of manufacturing semiconductor device
To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is...
US-9,356,151 Fabrication of graphene nanoribbons and nanowires using a meniscus as an etch mask
In some embodiments, the present disclosure pertains to methods of preparing graphene nanoribbons from a graphene film associated with a meniscus, where the...
US-9,356,150 Method for incorporating impurity element in EPI silicon process
The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each...
US-9,356,149 Silicide protection during contact metallization and resulting semiconductor structures
A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source...
US-9,356,148 Fin-type semiconductor device and manufacturing method
One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part...
US-9,356,147 FinFET spacer etch for eSiGe improvement
A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided....
US-9,356,146 Semiconductor device with recess, epitaxial source/drain region and diffuson
A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode,...
US-9,356,145 Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-9,356,144 Remote gate protection diode for field effect transistors
The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over...
US-9,356,143 Semiconductor device and manufacturing method thereof
A semiconductor device includes: an n-type first source region and first drain region formed in a surface of a p-type epitaxial layer; an n-type first source...
US-9,356,142 Pattern layout to prevent split gate flash memory cell failure
A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first...
US-9,356,141 Semiconductor device having peripheral trench structures
The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes...
US-9,356,140 Semiconductor device
A device comprises a substrate, an n-layer and a p-layer, an n-electrode, and a p-electrode. A step is formed at an outer circumference of the device. A...
US-9,356,139 Power MOSFETs and methods for forming the same
Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift...
US-9,356,138 Semiconductor device
There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with...
US-9,356,137 Power MOS device structure
Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of...
US-9,356,136 Engineered source/drain region for n-Type MOSFET
Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below...
US-9,356,135 Semiconductor device and method of manufacturing the same
To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure,...
US-9,356,134 Charged balanced devices with shielded gate trench
This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer...
US-9,356,133 Medium voltage MOSFET device
A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are...
US-9,356,132 Integrating Schottky diode into power MOSFET
A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield...
US-9,356,131 Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain...
The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k...
US-9,356,130 HEMT with compensation structure
A high electron mobility transistor includes a source, a gate and a drain, a first III-V semiconductor region, and a second III-V semiconductor region below the...
US-9,356,129 Tunnel junction field effect transistors having self-aligned source and gate electrodes and methods of forming...
Methods of forming a transistor include providing a semiconductor epitaxial structure including a channel layer and barrier layer on the channel layer, forming...
US-9,356,128 Semiconductor power device
A semiconductor power device, comprising: a substrate; a first semiconductor layer with a first lattice constant formed on the substrate; a first grading layer...
US-9,356,127 Layout structure of heterojunction bipolar transistors
A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive...
US-9,356,125 Manufacturing method of semiconductor structure
A manufacturing method of a semiconductor structure includes the following steps. A high-k dielectric layer is formed on a semiconductor substrate, and a...
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