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Memory array having divided apart bit lines and partially divided bit line
A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by...
Semiconductor device including air gaps and method of fabricating the same
A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line...
Resistive random access memory (RRAM) structure
A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode having an upper surface coplanar...
Methods of forming patterns and methods of manufacturing semiconductor
devices using the same
An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a...
This disclosure discloses a light-emitting display module display. The light-emitting display module comprises: a board; and a plurality of light-emitting diode...
Photo diode and method of forming the same
A method for forming a photo diode is provided. The method includes: forming a first pair of electrodes and a second pair of electrodes over a substrate by...
Image sensor and method for fabricating the same
An image sensor may include a substrate having photoelectric conversion regions respectively formed on a plurality of pixels and charge trap regions overlapping...
Image sensors including a gate electrode surrounding a floating diffusion
Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may...
Interconnect structure for stacked device and method
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor...
Image sensor having improved light utilization efficiency
An image sensor includes a first pixel row including a plurality of first pixels configured to sense first wavelength light, the first wavelength light having a...
Solid state imaging device and manufacturing method, and electronic
A solid state imaging device includes a substrate, in which the substrate includes a photoelectric conversion unit that generates a charge according to a light...
Image sensor, production apparatus, production method, and electronic
Provided is an image sensor including a photoelectric conversion unit for converting a received light into an electric charge; a semiconductor substrate...
Optoelectronic photodetector (variants)
A optoelectronic photo sensor to obtain single mosaic digital photographic images. Photo sensor is designed as a plurality of identical lenses having rows of...
Image sensor with buried light shield and vertical gate
A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a...
Image sensor device and method
A system and method for blocking light from regions around a photodiode in a pixel of an image sensor is provided. In an embodiment a first optical block layer...
BSI image sensor chips and methods for forming the same
A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate....
Backside structure for BSI image sensor
An embodiment method for forming an image sensor includes forming an anti-reflective coating over a surface of a semiconductor supporting a photodiode, forming...
Solid-state imaging apparatus and electronic device
Disclosed herein is a solid-state imaging apparatus including: a semiconductor base; a photodiode created on the semiconductor base and used for carrying out...
Solid-state imaging device, imaging apparatus, and method of driving the
solid-state imaging device
A solid-state imaging device including a semiconductor substrate; plural photoelectric conversion units formed side by side on the semiconductor substrate to...
Array substrate and method for fabricating the same, and display device
The present invention discloses an array substrate and a manufacturing method for the same, and a display device. By adopting the manufacturing method for the...
A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided. A semiconductor...
Thin film transistor array substrate and driving method therefor as well
as liquid crystal display
A thin film transistor array substrate, a driving method therefore, and a liquid crystal display are disclosed. The thin film transistor array substrate...
Thin film transistor with integrated connecting portion
A semiconductor device (100) according to the present invention includes a thin film transistor (10) having a gate electrode (62a), a first insulating layer...
A pixel array includes a plurality of first and second signal lines, a plurality of active devices, a plurality of pixel electrodes, a plurality of selection...
Display apparatus and method of manufacturing the same
A display apparatus includes a substrate; a cavity layer; a display material layer; and a capping layer. The cavity layer includes a plurality of barriers...
Display device with a transistor on an outer side of a bent portion
A non-breakable display device, electronic appliance, or lighting device is provided. A bendable display device in which a first flexible substrate and a second...
Light emitting device
It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over...
Integrated circuits with self aligned contact structures for improved
windows and fabrication methods
Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance:...
Structure and method for forming CMOS with NFET and PFET having different
Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium...
Semiconductor structure having column III-V isolation regions
A semiconductor structure provided having: a dielectric; a non-column III-V doped semiconductor layer disposed over the dielectric; and an isolation barrier...
Vertical type memory device
A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to...
Three-dimensional memory devices containing memory stack structures with
position-independent threshold voltage
The threshold voltage for vertical transistors in three-dimensional memory stack structures can be made independent of a lateral distance from a source region...
Non-volatile semiconductor storage device and method of manufacturing the
A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected...
3-D nonvolatile memory device and method of manufacturing the same
A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers...
Junction formation for vertical gate 3D NAND memory
A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed...
Nonvolatile memory device including a source line having a
A nonvolatile memory device includes a source line having a shape of a three-dimensional (3D) cap. The nonvolatile memory device includes a first vertical...
Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs,...
Memory architecture of 3D array with interleaved control structures
A 3D memory device includes a first plurality and a second plurality of stacks of semiconductor material strips on a substrate. The second plurality of stacks...
Semiconductor apparatus and manufacturing method of the same
A semiconductor apparatus according to an embodiment may include a first pipe gate divided by an isolation layer, a first pipe channel layer buried in the first...
Embedded SONOS based memory cells
A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first...
Multilevel interconnect structure and methods of manufacturing the same
A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first...
Three-dimensional semiconductor memory devices and methods of forming the
Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack...
Semiconductor device with improved electrode isolation
A floating gate insulating film is formed in a first element formation region of a substrate. A first insulating film and a control gate electrode are...
Three dimensional NAND string memory devices with voids enclosed between
control gate electrodes
A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching...
Method for manufacturing semiconductor device having antifuse with
semiconductor and insulating films as...
An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory...
Semiconductor device having buried gate, method of fabricating the same,
and module and system having the same
A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate...
Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various...
Dual work function integration for stacked FinFET
A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked...
Semiconductor device and semiconductor device manufacturing method
A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain...
Enhancing MOSFET performance with corner stresses of STI
The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of:...