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| Patent # | Description |
|---|---|
| US-9,355,973 |
Packaged semiconductor devices, methods of packaging semiconductor
devices, and PoP devices Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of... |
| US-9,355,972 |
Method for making a dielectric region in a bulk silicon substrate
providing a high-Q passive resonator Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive... |
| US-9,355,971 |
EOS protection for integrated circuits In some embodiment, a fuse structure in a semiconductor device uses a metal fuse element connected to a stacked via fuse link connected to a thin film resistive... |
| US-9,355,970 |
Chip package and method for forming the same An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A... |
| US-9,355,969 |
Semiconductor package A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package... |
| US-9,355,968 |
Silicon shield for package stress sensitive devices A surface mount semiconductor package, semiconductor device, and method for fabrication of the surface mount semiconductor package and electrical device are... |
| US-9,355,967 |
Stress compensation patterning An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to... |
| US-9,355,966 |
Substrate warpage control using external frame stiffener A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip... |
| US-9,355,965 |
Semiconductor devices and methods of making the same In one embodiment, methods for making semiconductor devices are disclosed. |
| US-9,355,964 |
Method for forming alignment marks and structure of same A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are... |
| US-9,355,963 |
Semiconductor package interconnections and method of making the same A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by... |
| US-9,355,962 |
Integrated circuit package stacking system with redistribution and method
of manufacture thereof A method of manufacture of an integrated circuit package stacking system including: forming a base frame includes: providing a support panel, and forming a... |
| US-9,355,961 |
Semiconductor devices having through-electrodes and methods for
fabricating the same A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor... |
| US-9,355,960 |
Electromagnetic bandgap structure for three dimensional ICS An electromagnetic bandgap (EBG) cell comprises a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wires on at... |
| US-9,355,959 |
Active chip on carrier or laminated chip having microelectronic element
embedded therein A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within... |
| US-9,355,958 |
Semiconductor device having a corrosion-resistant metallization and method
for manufacturing thereof A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge... |
| US-9,355,957 |
Semiconductor device with self-aligned contact plugs A semiconductor device includes subsurface structures extending from a main surface into a semiconductor portion, each subsurface structure including a gate... |
| US-9,355,956 |
Inductor for semiconductor integrated circuit An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive... |
| US-9,355,955 |
Semiconductor device A semiconductor device is provided in which reliability of the semiconductor device is improved by improving an EM characteristic, a TDDB characteristic, and a... |
| US-9,355,954 |
Capacitor in post-passivation structures and methods of forming the same A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying... |
| US-9,355,953 |
Vertical semiconductor MOSFET device with double substrate-side multiple
electrode connections and encapsulation A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with... |
| US-9,355,952 |
Device packaging with substrates having embedded lines and metal defined
pads Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer... |
| US-9,355,951 |
Interconnect layouts for electronic assemblies Embodiments of the present disclosure provide an apparatus including an electronic device and a substrate to receive the electronic device, the electronic... |
| US-9,355,950 |
Power semiconductor module having low gate drive inductance flexible board
connection A power semiconductor module includes a metallization layer and a power semiconductor die attached to the metallization layer. The die has a first terminal and... |
| US-9,355,948 |
Multi-function and shielded 3D interconnects A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality... |
| US-9,355,947 |
Printed circuit board having traces and ball grid array package including
the same A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower... |
| US-9,355,946 |
Converter having partially thinned leadframe with stacked chips and
interposer, free of wires and clips Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip... |
| US-9,355,945 |
Semiconductor device with heat-dissipating lead frame A packaged semiconductor device has a top and a bottom and includes a lead frame, a die, and an encapsulant that encapsulates the die and most of the lead... |
| US-9,355,944 |
Semiconductor device and lead frame having vertical connection bars A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a... |
| US-9,355,943 |
Manufacturing and evaluation method of a semiconductor device Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and... |
| US-9,355,942 |
Gang clips having distributed-function tie bars Gang clips (500) having a flat area (510), a ridge (510a), and tie bars (530b) extending from the flat area, the end portions of the ties bars aligned in a... |
| US-9,355,941 |
Semiconductor device with step portion having shear surfaces A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is... |
| US-9,355,940 |
Auxiliary leadframe member for stabilizing the bond wire process A semiconductor package comprises a die attach pad and an auxiliary support member at least partially circumscribing the die attach pad. A set of contact leads... |
| US-9,355,939 |
Integrated circuit package stacking system with shielding and method of
manufacture thereof A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a... |
| US-9,355,938 |
Conductive compositions and methods of using them A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially... |
| US-9,355,937 |
Semiconductor device A semiconductor device includes a semiconductor substrate, a first metal layer, a barrier metal layer, and a second metal layer. The semiconductor substrate... |
| US-9,355,936 |
Flattened substrate surface for substrate bonding Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip... |
| US-9,355,935 |
Connecting through vias to devices Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a... |
| US-9,355,934 |
Method and apparatus providing integrated circuit having redistribution
layer with recessed connectors A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to... |
| US-9,355,933 |
Cooling channels in 3DIC stacks An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect... |
| US-9,355,932 |
Heat dissipation structure for an integrated circuit (IC) chip An apparatus for cooling an integrated circuit (IC) die is described. The apparatus includes an adhesion layer coated on a surface of the IC die, wherein the... |
| US-9,355,931 |
Package-on-package devices and methods of manufacturing the same Package-on-package (POP) devices and methods of manufacturing the POP devices are provided. In the POP devices, a thermal interface material layer disposed... |
| US-9,355,930 |
Semiconductor device A surface of a power semiconductor chip, mounted within a power semiconductor module and not being opposed to a wiring thin film, and a surface of a bonding... |
| US-9,355,929 |
Data storage based upon temperature considerations A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to... |
| US-9,355,928 |
Package-on-package structure A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the... |
| US-9,355,927 |
Semiconductor packaging and manufacturing method thereof The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The... |
| US-9,355,926 |
Curable composition Provided are a curable composition and its use. The curable composition can exhibit excellent processability and workability. The curable composition exhibits... |
| US-9,355,925 |
Photocoupler A photocoupler includes: a light emitting element; a light receiving element; an inner resin layer; and an outer resin layer. The light emitting element is... |
| US-9,355,924 |
Integrated circuit underfill scheme An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is... |
| US-9,355,923 |
Semiconductor device with an overlay mark including segment regions
surrounded by a pool region Disclosed herein is a semiconductor device that includes a plurality of segment regions arranged with a first distance, each of segment regions including a... |
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