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Patent # Description
US-9,355,922 Systems and methods for internal surface conditioning in plasma processing equipment
A method of conditioning internal surfaces of a plasma source includes flowing first source gases into a plasma generation cavity of the plasma source that is...
US-9,355,921 Test macro for use with a multi-patterning lithography process
A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming...
US-9,355,920 Methods of forming semiconductor devices and FinFET devices, and FinFET devices
Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming...
US-9,355,919 Methods and systems for inspecting bonded wafers
A method of inspecting a bonded wafer 3 arrangement comprises: directing measuring radiation through the bonded wafer arrangement 3; imaging at least a portion...
US-9,355,918 Method for producing high-purity polycrystalline silicon
The present invention provides technology for realizing higher purification of a polycrystalline silicon. First, trichlorosilane is prepared as a sample (S101)...
US-9,355,917 Complementary metal oxide semiconductor device, optical apparatus including the same, and method of...
A complementary metal oxide semiconductor (CMOS) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a...
US-9,355,916 Semiconductor manufacturing method and semiconductor device
A method manufactures a semiconductor device which allows nanocarbon materials, such as high-quality graphene and carbon nanotube to be used. The method of...
US-9,355,915 Integrate circuit with nanowires
A method includes providing a substrate having a metal-oxide-semiconductor (MOS) region. The MOS region includes first gate, source, and drain regions for a...
US-9,355,914 Integrated circuit having dual material CMOS integration and method to fabricate same
In one aspect thereof the invention provides a structure that includes a substrate having a surface and a plurality of fins supported by the surface of the...
US-9,355,913 3D semiconductor devices and methods of fabricating same
A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a...
US-9,355,912 Jog design in integrated circuits
A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and...
US-9,355,911 Fine patterning methods and methods of fabricating semiconductor devices using the same
A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the...
US-9,355,910 Semiconductor device with transistor local interconnects
A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first...
US-9,355,909 Method of manufacturing an integrated circuit having field effect transistors including a peak in a body dopant...
An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second...
US-9,355,908 Semiconductor pillar transistors having channels with different crystal orientations
According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and...
US-9,355,907 Hybrid wafer dicing approach using a line shaped laser beam profile laser scribing process and plasma etch process
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
US-9,355,906 Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device...
US-9,355,905 Methods and structure for carrier-less thin wafer handling
Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a...
US-9,355,904 Method for strain-relieved through substrate vias
A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via...
US-9,355,903 Semiconductor device with air gap and method for fabricating the same
A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the...
US-9,355,902 Method of fabricating semiconductor apparatus with through-silicon via and method of fabricating stack package...
In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon...
US-9,355,901 Non-lithographic formation of three-dimensional conductive elements
A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer...
US-9,355,900 Semiconductor device and method of manufacturing the same
A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole...
US-9,355,899 Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one...
US-9,355,898 Package on package (PoP) integrated device comprising a plurality of solder resist layers
Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder...
US-9,355,897 Methods of forming semiconductor structures
Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such...
US-9,355,896 Package systems
A package system includes a first substrate; and a second substrate electrically coupled with the first substrate. The package system further includes a...
US-9,355,895 Method of providing a via hole and routing structure
A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the...
US-9,355,894 Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a...
US-9,355,893 Method for preventing extreme low-K (ELK) dielectric layer from being damaged during plasma process
A method for forming an interconnect structure is provided. The method includes providing a substrate. The method also includes forming a dielectric layer on...
US-9,355,892 Integrated circuit structure with active and passive devices in different tiers
An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a...
US-9,355,891 Method for exposing a layer
A method for exposing a layer buried in a substrate via a trench having an insulated lateral wall and an insulated floor includes the steps of applying an oxide...
US-9,355,890 Method of manufacturing semiconductor device and semiconductor device
Disclosed is a miniaturized semiconductor device having an SOI layer, in which: a silicon layer is formed over a semiconductor substrate via an BOX film; after...
US-9,355,889 Semiconductor-on-insulator device and method of fabricating the same
The disclosed technology generally relates to semiconductor-on-insulator (SOI) devices and more particularly to SOI devices having a channel region comprising a...
US-9,355,888 Implant isolated devices and method for forming the same
A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor...
US-9,355,887 Dual trench isolation for CMOS with hybrid orientations
The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid...
US-9,355,886 Conformal film deposition for gapfill
A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or...
US-9,355,885 Wafer support device
A wafer support device is provided. The wafer support device includes a plurality of support portions; and a bottom area located among the support portions,...
US-9,355,884 Installation fixture for elastomer bands and methods of using the same
A kit comprising an installation fixture, a plurality of mechanical fasteners and an embedding tool is provided which allows for an elastomer band to be...
US-9,355,883 Method and apparatus for liquid treatment of wafer shaped articles
In an apparatus and method for treating a wafer-shaped article, a spin chuck is provided for holding a wafer-shaped article in a predetermined orientation...
US-9,355,882 Transfer module for bowed wafers
A wafer grinding system includes a robot arm having a suction board at one end and a table within reach of the robot arm. An upper surface of the table has a...
US-9,355,881 Semiconductor device including a dielectric material
A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the...
US-9,355,880 Method and apparatus for the transporting of objects
The present invention relates to methods and apparatuses for the transporting of substantially flat, freely movable objects, wherein at least the holding and...
US-9,355,879 Substrate transfer robot, substrate transfer system, and method for detecting arrangement state of substrate
A substrate transfer robot includes a hand and a controller. The hand includes at least one detector configured to detect an arrangement state of a substrate in...
US-9,355,878 Substrate processing apparatus
Disclosed is a substrate processing apparatus including first and second chambers stacked one above the other; a first opening that is provided in a wall of the...
US-9,355,877 Carrier substrate, method of manufacturing the same, and method of manufacturing flexible display device using...
A carrier substrate includes: a base substrate; a first coating layer on a first surface of the base substrate; and a second coating layer on a second surface...
US-9,355,876 Process load lock apparatus, lift assemblies, electronic device processing systems, and methods of processing...
A process load lock apparatus is disclosed. The process load lock apparatus includes a load lock chamber adapted to couple between a mainframe section and a...
US-9,355,875 Liquid processing apparatus
Liquid processing units 2 each for performing a liquid process on a substrate are arranged horizontally side by side, a gas exhaust pipe 3 for exhausting an...
US-9,355,874 Silicon nitride etching in a single wafer apparatus
A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride...
US-9,355,873 Apparatuses, systems and methods for cleaning photovoltaic devices
Embodiments of solar panel cleaning apparatuses, solar panel cleaning systems, and solar panel cleaning methods are disclosed. In certain embodiments, the...
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