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Patent # Description
US-9,355,066 Accelerated calculation of array statistics
The present disclosure describes systems and techniques relating to calculation of array statistics. According to an aspect of the described systems and...
US-9,355,065 System for gathering data from an industrial vehicle
Operation of an industrial vehicle is managed by systems onboard that vehicle. One such management system monitors operation of vehicle components and produces...
US-9,355,064 Tracking vehicle locations in a parking lot for definitive display on a GUI
A computer implemented method for displaying on a map a definitive image of precise locations of multiple mobile objects such as vehicles in a lot. The lot is...
US-9,355,063 Parking lot detection using probe data
Parking lot (18, 20) locations and geometries are discerned from probe data (22) and integrated with a digital map (12) for use in navigation and other...
US-9,355,062 Method and system for evaluation of fire suppression systems performance
An initial (near-field) spray generated by a sprinkler under study is fully characterized using a laser-supported Shadowgraphy/PTV system. Near-field spray...
US-9,355,061 Data processing apparatus and method for performing scan operations
A data processing apparatus and method are provided for executing a vector scan instruction. The data processing apparatus comprises a vector register store...
US-9,355,060 Storage service lifecycle policy transition management
Methods and apparatus for storage lifecycle configuration management are disclosed. A storage medium stores program instructions that, when executed on a...
US-9,355,059 Automating user's operations
To select a communication sequence for automating user's operations, a system performing a user's operation is provided, which acquires and stores a...
US-9,355,058 High performance interconnect physical layer
A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical...
US-9,355,057 Universal serial bus repeater
A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first...
US-9,355,056 Communication apparatus with slew rate feedback
In accordance with one or more example aspects of the disclosure, communications are effected on a bus using bit time and slew rate feedback. As consistent with...
US-9,355,055 Network and power connection management
The use of asset connectivity verification and switchable asset connectivity activation techniques may reduce or eliminate occurrences of human errors with...
US-9,355,054 Digital calibration-based skew cancellation for long-reach MIPI D-PHY serial links
A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial...
US-9,355,053 PCIe SMBus slave address self-selection
Embodiments of the invention describe an apparatus, system and method for slave devices to "self-select" their own Inter-Integrated Circuit/System Management...
US-9,355,052 Dynamically resizing direct memory access (DMA) windows
A dynamic DMA window mechanism can resize DMA windows dynamically by increasing one DMA window at the expense of reducing a neighboring DMA window. The dynamic...
US-9,355,051 Apparatus, method, and manufacture for using a read preamble to optimize data capture
A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data...
US-9,355,050 Secure, fast and normal virtual interrupt direct assignment in a virtualized interrupt controller in a mobile...
Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical...
US-9,355,049 Interrupt monitoring system and computer system
An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit...
US-9,355,048 Method for implementing secure data channel between processor and devices
Apparatuses, systems, and methods are directed to securely store, transfer, and/or process data especially sensitive data sent from input devices to processors....
US-9,355,047 Method and devices for controlling operations of a central processing unit
Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to...
US-9,355,046 Information processing apparatus, information processing method, and computer-readable medium
An information processing apparatus comprises: a display unit configured to display, on a display device, a virtual device object to which a first object of a...
US-9,355,045 Memory device for converting data received from controller controlling reading and writing of data
According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an...
US-9,355,044 System and method for protecting data stored on a removable data storage device
A system for protecting data stored in a removable data storage device includes a personal electronic device, a removable solid state data storage device...
US-9,355,043 Cache replacement method and system
A system, computer readable medium and method for managing objects in a cache. The method includes receiving a request for a desired object that is not stored...
US-9,355,042 Managing a translation lookaside buffer
Method and apparatus for managing a translation lookaside buffer (TLB) at hardware in a virtualization enabled system. According to embodiments of the present...
US-9,355,041 Frame buffer access tracking via a sliding window in a unified virtual memory system
One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding...
US-9,355,040 Adjunct component to provide full virtualization using paravirtualized hypervisors
A system configuration is provided with a paravirtualizing hypervisor that supports different types of guests, including those that use a single level of...
US-9,355,039 Application-directed memory de-duplication
In a computing system including an application executing on top of a virtualization control layer, wherein the virtualization control layer maps portions of a...
US-9,355,038 Cache bank spreading for compression algorithms
Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an...
US-9,355,037 Populating items in worklists using existing cache
Methods, systems, and computer-readable storage media for providing a worklist of a user with at least one item. In some implementations, actions include...
US-9,355,036 System and method for operating a system to cache a networked file system utilizing tiered storage and...
A network attached storage (NAS) caching appliance, system, and associated method of operation for caching a networked file system. Still further, some...
US-9,355,035 Dynamic write priority based on virtual write queue high water mark for set associative cache using cache...
A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue,...
US-9,355,034 Removal and optimization of coherence acknowledgement responses in an interconnect
According to one general aspect, a method of performing a cache transaction may include transmitting a cache request to a target device. The method may include...
US-9,355,033 Supporting multiple types of guests by a hypervisor
A system configuration is provided that includes multiple partitions that have differing translation mechanisms associated therewith. For instance, one...
US-9,355,032 Supporting multiple types of guests by a hypervisor
A system configuration is provided that includes multiple partitions that have differing translation mechanisms associated therewith. For instance, one...
US-9,355,031 Techniques for mapping device addresses to physical memory addresses
A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component...
US-9,355,030 Parallel garbage collection implemented in hardware
Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing...
US-9,355,029 Thread-based memory management with garbage collection
Systems and methods for thread-based memory management may include activating a processing thread. The memory may include a first region and a second region...
US-9,355,028 Data-storage device and flash memory control method
A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information,...
US-9,355,027 Zone-based defragmentation methods and user devices using the same
A defragmentation method of a user device which includes a host and a nonvolatile storage device includes: determining whether fragments of a first file stored...
US-9,355,026 Searching using multilevel cells and programming multilevel cells for searching
Methods of searching and methods of programming a memory are provided. In one such method of searching, a determination is made as to whether an attribute of a...
US-9,355,025 Method of controlling memory system in the event of sudden power off
A method of controlling a memory system that comprises a first flash memory device and a memory controller, the method comprising counting a first timeout when...
US-9,355,024 Systems and methods for nonvolatile memory performance throttling
Systems and methods for nonvolatile memory ("NVM") performance throttling are disclosed. Performance of an NVM system may be throttled to achieve particular...
US-9,355,023 Virtual address pager and method for use with a bulk erase memory
A virtual address pager and method for use with a bulk erase memory is disclosed. The virtual address pager includes a page protection controller configured...
US-9,355,022 Systems and methods for intelligent flash management
Systems and method for performing intelligent flash management are disclosed. A controller may determine if a write pattern exists between a set of writes...
US-9,355,021 Cross-threaded memory system
In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to...
US-9,355,020 Resolving nondeterminism in application behavior models
Methods, systems, and computer-readable storage media for resolving nondeterminism in a behavior model of a computing system under test (SUT). In some...
US-9,355,019 Method for test case reduction based on program behavior slices
The present invention provides a method of test cases reduction based on program behavior slices. In the present invention, during a static analysis stage,...
US-9,355,018 History N-section for property location
A test system controller receives a test code having N versions, selects n intermediate versions of the test code, and tests the test code using history...
US-9,355,017 Automated error checking system for a software application and method therefor
A test system for providing automatic testing of an application on a plurality of devices, the system including an input/output device for communicating with...
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