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Patent # Description
US-9,362,422 Semiconductor device and method for fabricating the same
Provided is a semiconductor device and a method for fabricating the same. The semiconductor device includes an interlayer insulating layer formed on a...
US-9,362,421 Semiconductor device including a support structure
In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed...
US-9,362,420 Transistor structure for electrostatic discharge protection
The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped...
US-9,362,419 Variable resistance device having parallel structure
A variable resistance device includes a parallel structure. The variable resistance device is formed using a silicon (Si) substrate. In the variable resistance...
US-9,362,418 Semiconductor structures including bodies of semiconductor material and methods of forming same
Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from...
US-9,362,417 Semiconductor device
To provide a highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics. The...
US-9,362,416 Semiconductor wearable device
One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate...
US-9,362,415 Semiconductor device comprising a transistor comprising an oxide semiconductor layer
Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in...
US-9,362,414 Oxide thin film transistor, display device, and method for manufacturing array substrate
Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A...
US-9,362,413 MOTFT with un-patterned etch-stop
A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide...
US-9,362,412 Semiconductor device
One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output...
US-9,362,411 Semiconductor device and manufacturing method thereof
An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device...
US-9,362,410 Semiconductor device, manufacturing method thereof, and display device
A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction...
US-9,362,409 Semiconductor device
A manufacturing method of a display device having an array substrate includes the steps of forming a projection of an organic material in a pixel on the array...
US-9,362,408 Thin film transistor and display panel including the same
Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and...
US-9,362,407 Symmetrical extension junction formation with low-K spacer and dual epitaxial process in FinFET device
A technique relates to a dual epitaxial process a device. A first spacer is disposed on a substrate, dummy gate, and hardmask. A first area extends in a first...
US-9,362,406 Faceted finFET
Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A...
US-9,362,405 Channel cladding last process flow for forming a channel region on a FinFET device
One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi...
US-9,362,404 Doping for FinFET
First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of...
US-9,362,403 Buried fin contact structures on FinFET semiconductor devices
A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of...
US-9,362,402 Semiconductor devices and fabrication method thereof
A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the...
US-9,362,401 Semiconductor device
A semiconductor device includes a substrate, a buffer layer provided on the substrate, a channel layer provided on the buffer layer, an electron supply layer...
US-9,362,400 Semiconductor device including dielectrically isolated finFETs and buried stressor
A finFET semiconductor device includes a semiconductor-on-insulator (SOI) substrate including a buried insulator layer, a plurality of semiconductor fins on the...
US-9,362,399 Well implant through dummy gate oxide in gate-last process
The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor...
US-9,362,398 Low resistance LDMOS with reduced gate charge
An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first...
US-9,362,397 Semiconductor devices
A gate-all-around (GAA) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source...
US-9,362,396 Semiconductor device, manufacturing method thereof, electronic device and vehicle
A method for manufacturing a semiconductor device, includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film...
US-9,362,395 High-voltage field-effect transistor and method of making the same
The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region...
US-9,362,394 Power device termination structures and methods
Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate...
US-9,362,393 Vertical semiconductor device including element active portion and voltage withstanding structure portion, and...
Aspects of the invention are directed to a vertical semiconductor device including an element active portion and a voltage withstanding structure portion that...
US-9,362,392 Vertical high-voltage semiconductor device and fabrication method thereof
To provide a vertical SIC-MOSFET and IGBT capable of having low ON-resistance without destruction of gate oxide films or degradation of reliability even when a...
US-9,362,391 Silicon carbide semiconductor device and method of manufacturing the same
It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a...
US-9,362,390 Logic elements comprising carbon nanotube field effect transistor (CNTFET) devices and methods of making same
Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field...
US-9,362,389 Polarization induced doped transistor
A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and...
US-9,362,388 Testing of LDMOS device
A method for testing an LDMOS transistor by measuring leakage current between the source and drain in the presence of a bias voltage. The leakage current is...
US-9,362,387 Method for producing multi-gate in FIN field-effect transistor
A method for producing a multi-gate fin field-effect transistor (FinFET) is provided. The method includes forming a channel layer and a gate medium layer on a...
US-9,362,386 FETs and methods for forming the same
FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and...
US-9,362,385 Method for tuning threshold voltage of semiconductor device with metal gate structure
A method for manufacturing a metal gate structure includes forming a high-k dielectric layer in a gate trench; forming an etch stop over the high-k dielectric...
US-9,362,384 Double diffused metal oxide semiconductor device and manufacturing method thereof
The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first...
US-9,362,383 Highly scaled tunnel FET with tight pitch and method to fabricate same
A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying...
US-9,362,382 Method for forming semiconductor device with low sealing loss
A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal...
US-9,362,381 Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate and manufacturing...
The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN)...
US-9,362,380 Heterojunction bipolar transistor
The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation...
US-9,362,379 Graphene heterostructure field effect transistors
A field effect transistor includes a substrate, a first graphene (Gr) layer on the substrate, a second graphene (Gr) layer on the substrate, a fluorographene...
US-9,362,378 Piezoelectric devices and methods for their preparation and use
Methods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a...
US-9,362,377 Low line resistivity and repeatable metal recess using CVD cobalt reflow
Methods for forming a semiconductor gate electrode with a reflowed Co layer and the resulting device are disclosed. Embodiments include forming a trench in an...
US-9,362,376 Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at...
US-9,362,375 Inner L-spacer for replacement gate flow
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner...
US-9,362,374 Simple and cost-free MTP structure
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. A non-volatile MTP memory cell...
US-9,362,373 Semiconductor device and the method of manufacturing the same
A semiconductor device includes a semiconductor substrate which functions as an n.sup.- drift layer, a trench IGBT formed in the front surface, an interlayer...
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