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Patent # Description
US-9,362,321 Solid-state imaging device and manufacturing method thereof
A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion...
US-9,362,320 Integrated circuit having a level shifter and method of making the same
Integrated circuit (IC), and method of forming an IC, in which a photodiode having a photodiode output is coupled to a column line. A transfer transistor is...
US-9,362,319 Image pickup device
An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate....
US-9,362,318 Method of manufacturing a semiconductor device
An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an...
US-9,362,317 Display device and electronic unit
A display device includes: a substrate including a display region and a peripheral region; a first wiring provided on a front face of the substrate; and a...
US-9,362,316 Display device
Disclosed is a display device which includes: a plurality of gate lines arranged in a first direction; a plurality of data lines arranged in a second direction...
US-9,362,314 Thin film transistor substrate
A thin film transistor substrate is disclosed, which comprises: a substrate; and plural thin film transistor (TFT) units, an insulating layer, a pixel electrode...
US-9,362,313 Thin film transistor and display device
Provided is an oxide-semiconductor-based thin film transistor having satisfactory switching characteristics and stress resistance. Change in threshold voltage...
US-9,362,312 Semiconductor device, display unit, and electronic apparatus
Provided is a semiconductor device that includes a transistor. The transistor includes: a gate electrode; an oxide semiconductor film facing the gate electrode...
US-9,362,311 Method of fabricating semiconductor device
A method of fabricating a semiconductor device is provided. A first semiconductor layer including Ge at a first concentration is formed on an insulation layer....
US-9,362,310 Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET...
A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial...
US-9,362,309 FinFET and method of fabrication
An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110}...
US-9,362,308 Semiconductor device having finFET structures and method of making same
A semiconductor device and method making it comprises pFETs with an SiGe channel and nFETs with an Si channel, formed on an SOI substrate. Improved uniformity...
US-9,362,307 Thin film transistor, electronic device having the same, and method for manufacturing the same
An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving...
US-9,362,306 Semiconductor device and method of fabricating the same
According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on...
US-9,362,305 Vertically stacked nonvolatile NAND type flash memory device with U-shaped strings, method for operating the...
A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second...
US-9,362,304 Nonvolatile memory device and method of fabricating the same
This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate...
US-9,362,303 Semiconductor memory devices including fine patterns and methods of fabricating the same
Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a...
US-9,362,302 Source line formation in 3D vertical channel and memory
A memory device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom level of conductive strips, a...
US-9,362,301 Method for fabricating pipe gate nonvolatile memory device
A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell...
US-9,362,300 Apparatuses and methods for forming multiple decks of memory cells
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
US-9,362,299 Method of fabricating a nonvolatile memory device with a vertical semiconductor pattern between vertical source...
A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel...
US-9,362,298 Non-volatile semiconductor memory device and manufacturing method thereof
This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a...
US-9,362,297 Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same
Integrated circuits are provided. An exemplary integrated circuit includes a source/drain region in a semiconductor substrate. The integrated circuit includes a...
US-9,362,296 Non-volatile memory semiconductor devices and method for making thereof
The disclosed technology generally relates to memory devices, and more particularly to memory devices having an intergate dielectric stack comprising multiple...
US-9,362,295 Semiconductor storage device and method for manufacturing the semiconductor storage device
A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a...
US-9,362,294 Semiconductor device including an electrode lower layer and an electrode upper layer and method of...
The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has...
US-9,362,293 CT-NOR differential bitline sensing architecture
Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory...
US-9,362,292 Two-port SRAM cell structure for vertical devices
Two-Port SRAM cells are described. In an embodiment, a cell includes first, second, and read-port pull-down, first and second pull-up, first, second, and...
US-9,362,291 Integrated circuit devices and methods
An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two...
US-9,362,290 Memory cell layout
A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once...
US-9,362,289 Semiconductor device including landing pad
The semiconductor device includes a plurality of conductive line structures including a plurality of conductive lines spaced apart from a substrate with an...
US-9,362,288 Semiconductor device and manufacturing method thereof
One semiconductor device includes an active region extending in a first direction, and first, second, and third semiconductor pillars which are provided upright...
US-9,362,287 Semiconductor device and method for manufacturing the same
A semiconductor device includes: a first transistor and a second transistor disposed in or on a silicon substrate; an element isolation structure that isolates...
US-9,362,286 Fin field effect transistor and method for forming the same
Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A...
US-9,362,285 Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs
Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET)...
US-9,362,284 Threshold voltage control for mixed-type non-planar semiconductor devices
A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the...
US-9,362,283 Gate structures for transistor devices for CMOS applications and products
An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer...
US-9,362,282 High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V...
An electrical device that includes a substrate including a first region of a type III-V semiconductor material and a second region of a type IV germanium...
US-9,362,281 Group III nitride integration with CMOS technology
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The...
US-9,362,280 Semiconductor devices with different dielectric thicknesses
An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the...
US-9,362,279 Contact formation for semiconductor device
A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a...
US-9,362,278 FinFET with multiple dislocation planes and method for forming the same
A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second...
US-9,362,277 FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a...
US-9,362,276 Semiconductor device and fabrication method
Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is...
US-9,362,275 Semiconductor device with dummy gate structures
A semiconductor and a method for manufacturing the semiconductor device are provided. A semiconductor substrate is provided. A first oxide layer is formed over...
US-9,362,274 Self-aligned contact for replacement metal gate and silicide last processes
A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k...
US-9,362,273 Semiconductor device and method of manufacturing the same
There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely...
US-9,362,272 Lateral MOSFET
A lateral MOSFET comprises a plurality of isolation regions formed in a substrate, wherein a first isolation region is of a top surface lower than a top surface...
US-9,362,271 Capacitive device
A capacitive device includes a substrate, a well structure buried in the substrate, a first stacked layer that includes a first dielectric layer and a first...
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