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Patent # Description
US-9,362,270 High sheet resistor in CMOS flow
An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with...
US-9,362,269 Resistor and metal-insulator-metal capacitor structure and method
A passive circuit device incorporating a resistor and a capacitor and a method of forming the circuit device are disclosed. In an exemplary embodiment, the...
US-9,362,268 Semiconductor integrated circuit device with transistor and non-transistor regions
In a high-frequency circuit, it is necessary to provide galvanic blocking between active elements such as transistors and between an active element and an...
US-9,362,267 Group III-V and group IV composite switch
In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source...
US-9,362,266 Electrostatic discharge protection device for differential signal devices
A robust electrostatic (ESD) protection device is provided. In one example, the ESD protection device is configured to accommodate three nodes. When used with a...
US-9,362,265 Protection devices for precision mixed-signal electronic circuits and methods of forming the same
Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a...
US-9,362,264 Semiconductor device comprising a plurality of cell arrays including a well potential supply region and...
A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region...
US-9,362,263 Semiconductor device
This invention can reduce heat that is generated in a first semiconductor chip and transfers to a second semiconductor chip through through-silicon vias. The...
US-9,362,262 Semiconductor device
This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming...
US-9,362,261 Power semiconductor module
The purpose of the present invention is to reduce the wiring inductance of a power semiconductor module. It comprises a first power semiconductor device, a...
US-9,362,260 Stacked packaged integrated circuit devices, and methods of making same
A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged...
US-9,362,259 Discontinuous patterned bonds for semiconductor devices and associated systems and methods
Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second...
US-9,362,258 Optoelectronic component having chips and conversion elements
An optoelectronic component includes a carrier, a first optoelectronic semiconductor chip arranged on the carrier, a first conversion element arranged on the...
US-9,362,257 Mirco-electro-mechanical system module and manufacturing method thereof
The invention provides a micro-electro-mechanical system (MEMS) module, which includes a MEMS die stacked on an electronic circuit die. The electronic circuit...
US-9,362,256 Bonding process for a chip bonding to a thin film substrate
A bonding process for a chip bonded to a thin film substrate is disclosed. The thin film substrate has a thickness of about less than 500 um. Curvature occurs...
US-9,362,255 Method for manufacturing a multilayer structure on a substrate
The invention relates to a method for manufacturing a multilayer strucute on a first substrate, the method including: using the first substrate made of a first...
US-9,362,254 Wire bonding method and chip structure
A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least...
US-9,362,253 Bumpless build-up layer package with pre-stacked microelectronic devices
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL)...
US-9,362,252 Method and apparatus of ESD protection in stacked die semiconductor device
An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger...
US-9,362,251 Antioxidant gas blow-off unit
An antioxidant gas blow-off unit includes: a base portion configured as a hollow plate having an antioxidant gas flow passage formed therein; a hole that is...
US-9,362,250 Die bonder and bonding method
The present invention provides a bonding device and a bonding method with a high operation ratio by solving the problems of conventional techniques. In the...
US-9,362,249 Silver--gold alloy bonding wire
The silver-gold alloy bonding wire of the present invention includes an alloy composed of not lower than 10% and not higher than 30% of gold (Au) and not lower...
US-9,362,248 Coreless package structure and method for manufacturing same
A coreless package structure and a method for manufacturing same includes the steps of providing a supporting substrate comprising an etching resist layer and a...
US-9,362,247 Systems and methods for bonding semiconductor elements
A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first...
US-9,362,246 Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and...
A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers...
US-9,362,245 Package structure and fabrication method thereof
A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer...
US-9,362,244 Wire tail connector for a semiconductor device
A memory device, and a method of making the memory device, are disclosed. The memory device is fabricated by mounting one or more semiconductor die on a...
US-9,362,243 Semiconductor package device and forming the same
In some embodiments in accordance with the present disclosure, a semiconductor device having a semiconductor substrate is provided. A metal structure is...
US-9,362,242 Bonding structure including metal nano particle
A bonding structure including metal nano particles includes a first member having a metal surface on at least one side, a second member having a metal surface...
US-9,362,241 Manufacturing method for semiconductor devices
A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film...
US-9,362,240 Electronic device
An electronic device includes multiple semiconductor chips in a single housing. Such semiconductor chips may comprise different semiconductor materials, for...
US-9,362,239 Vertical breakdown protection layer
The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality...
US-9,362,238 Semiconductor device
A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a...
US-9,362,237 Air bridge structure having dielectric coating
A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions...
US-9,362,236 Package structures and methods for forming the same
A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally...
US-9,362,235 Semiconductor package
A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the...
US-9,362,234 Shielded device packages having antennas and related fabrication methods
Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding...
US-9,362,233 Radio frequency shielding within a semiconductor package
Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and...
US-9,362,232 Apparatus and method for embedding components in small-form-factor, system-on-packages
According to various aspects of the present disclosure, an apparatus is disclosed that includes a small form factor mobile platform including a ...
US-9,362,231 Molecular self-assembly in substrate processing
Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to...
US-9,362,230 Methods to form conductive thin film structures
Electrically conductive structures and methods of making electrically conductive structures. The methods include providing a dielectric layer of a material...
US-9,362,229 Semiconductor devices with enhanced electromigration performance
Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line...
US-9,362,228 Electro-migration enhancing method for self-forming barrier process in copper metalization
A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a...
US-9,362,227 Topological insulator in IC with multiple conductor paths
A topological insulator is grown on an IC wafer in a vacuum chamber as a thin film interconnect between two circuits in the IC communicating with each other. As...
US-9,362,226 Three-dimensional (3D) semiconductor devices and methods of fabricating 3D semiconductor devices
A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a...
US-9,362,225 Data storage device and methods of manufacturing the same
Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a...
US-9,362,224 Electrical fuse and method of fabricating the same
An electrical fuse is provided. The electrical fuse includes an anode formed on a substrate, a cathode formed on the substrate, a fuse link connecting the anode...
US-9,362,223 Integrated circuit assembly with cushion polymer layer
A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor...
US-9,362,222 Interconnection between inductor and metal-insulator-metal (MIM) capacitor
Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal-insulator-metal (MIM)...
US-9,362,221 Surface mountable power components
According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically...
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