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Patent # Description
US-9,362,220 Semiconductor device
A semiconductor device, including a substrate having an active region defined therein, a plurality of bit lines extending on the substrate in a first direction,...
US-9,362,219 Semiconductor module and semiconductor device
A heat sink has a fixation surface and a heat release surface opposite from the fixation surface. A fin is provided in a central portion of the heat release...
US-9,362,218 Integrated passive device (IPD) on substrate
Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to...
US-9,362,217 Package on package structure and fabrication method thereof
A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in...
US-9,362,216 Conductive pads and methods of formation thereof
In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive...
US-9,362,215 Power quad flat no-lead (PQFN) semiconductor package with leadframe islands for multi-phase power inverter
According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a U-phase output node situated on a first leadframe island of a...
US-9,362,214 Pre-encapsulated etching-then-plating lead frame structure with island and method for manufacturing the same
A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back...
US-9,362,212 Integrated circuit package having side and bottom contact pads
A packaged integrated circuit device includes a substrate module, leads, an IC die having first and second sets of die contact pads, and an encapsulant. The...
US-9,362,211 Exposed pad integrated circuit package with mold lock
An integrated circuit package has an exposed die pad with a trench and openings in the trench that are filled with encapsulant to form an encapsulant ring near...
US-9,362,210 Leadframe and semiconductor package made using the leadframe
Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the...
US-9,362,209 Shielding technique for semiconductor package including metal lid
In accordance with the present invention, there is provided a semiconductor package wherein a metal lid of the package is used as a shield that effectively...
US-9,362,208 Packaged semiconductor components having substantially rigid support members and methods of packaging...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
US-9,362,207 Metal wiring of semiconductor device and method for manufacturing the same
A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region...
US-9,362,206 Chip and manufacturing method thereof
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at...
US-9,362,205 Circuit device
A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. A lead (30) and lead (28) though which...
US-9,362,204 Tunable composite interposer
A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a...
US-9,362,203 Staged via formation from both sides of chip
A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of...
US-9,362,202 Electronic device and method for manufacturing same
An electronic device includes: a support member; an electronic component stacked over the support member with a plurality of connections therebetween; and a...
US-9,362,201 Heat exchange structure and cooling device comprising such a structure
A heat exchange structure is provided, including a primary face provided with non-through holes formed in said face, the inner surface of the holes and the...
US-9,362,200 Heat sink in the aperture of substrate
A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is...
US-9,362,199 Chip thermal dissipation structure
Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back,...
US-9,362,198 Semiconductor devices with a thermally conductive layer and methods of their fabrication
An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate...
US-9,362,197 Molded underfilling for package on package devices
Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount...
US-9,362,196 Semiconductor package and mobile device using the same
According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip,...
US-9,362,195 Semiconductor device
Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor...
US-9,362,194 Semiconductor chip covered with sealing resin having a filler material
A semiconductor device includes a wiring substrate, a sealing resin layer formed on the wiring substrate out of a filler-containing resin and having a one-sided...
US-9,362,193 Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for...
A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation...
US-9,362,192 Semiconductor device comprising heat dissipating connector
According to one embodiment, the connector includes a first portion and a second portion. The first portion is provided on the second surface of the...
US-9,362,191 Encapsulated semiconductor device
A semiconductor device includes a carrier and a semiconductor chip disposed over the carrier. The semiconductor chip has a first surface and a second surface...
US-9,362,190 Semiconductor element, semiconductor device including the same, and method for manufacturing semiconductor element
To provide a semiconductor element that can have the high adhesion between a substrate made of an oxide or the like and a metal film, a semiconductor element...
US-9,362,189 Case including semiconductor nanocrystals, and optoelectronic device including the same
A case including a case main body, a matrix including a semiconductor nanocrystal, the matrix disposed in the case main body, and a sealant disposed on the case...
US-9,362,188 TSV scan cell comparator coupled to voltage reference and response
An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between...
US-9,362,187 Chip package having terminal pads of different form factors
A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip...
US-9,362,186 Polishing with eddy current feed meaurement prior to deposition of conductive layer
A method of controlling polishing includes storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of...
US-9,362,185 Uniformity in wafer patterning using feedback control
A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose...
US-9,362,184 Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting...
A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor...
US-9,362,183 Method of manufacturing semiconductor device
Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique...
US-9,362,182 Forming strained fins of different material on a substrate
A method, and the resulting structure, of forming two fins with different types of strain and material on the same substrate.
US-9,362,181 Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the...
One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the...
US-9,362,180 Integrated circuit having multiple threshold voltages
In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect...
US-9,362,179 Method to form dual channel semiconductor material fins
A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a...
US-9,362,178 FinFET including varied fin height
According to another embodiment, a semiconductor finFET device includes a semiconductor substrate. The finFET device further includes at least one first...
US-9,362,177 Nanowire semiconductor device
A method for forming a nanowire device comprises forming a fin on a substrate, depositing a first layer of insulator material on the substrate, etching to...
US-9,362,176 Uniform exposed raised structures for non-planar semiconductor devices
The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP...
US-9,362,175 Epitaxial growth of doped film for source and drain regions
Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided...
US-9,362,174 Device wafer processing method
A device wafer processing method includes, a groove forming step in which grooves with a predetermined depth are formed in the front side of a device wafer; a...
US-9,362,173 Method for chip package
Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip;...
US-9,362,172 Semiconductor devices having through-vias and methods for fabricating the same
The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened...
US-9,362,171 Through via contacts with insulated substrate
Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at...
US-9,362,170 Dielectric liner for a self-aligned contact via structure
At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active...
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