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Patent # Description
US-9,362,169 Self-aligned semiconductor fabrication with fosse features
The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods...
US-9,362,168 Non-volatile memory device and method for manufacturing same
According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first...
US-9,362,167 Method of supplying cobalt to recess
A method of supplying cobalt to a recess formed in an insulation film of an object to be processed is disclosed. In one embodiment, the method includes forming...
US-9,362,166 Method of forming copper wiring
A method of forming a copper wiring buried in a recess portion of a predetermined pattern formed in an interlayer insulation layer of a substrate is disclosed....
US-9,362,165 2D self-aligned via first process flow
A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are...
US-9,362,164 Hybrid interconnect scheme and methods for forming the same
A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k...
US-9,362,163 Methods and apparatuses for atomic layer cleaning of contacts and vias
Described are cleaning methods for removing contaminants from an electrical contact interface of a partially fabricated semiconductor substrate. The methods may...
US-9,362,162 Methods of fabricating BEOL interlayer structures
Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes,...
US-9,362,161 Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating...
US-9,362,160 SOI structure and method for utilizing trenches for signal isolation and linearity
Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an...
US-9,362,159 Manufacturing method for display device
A method of manufacturing a display device that includes: performing a surface treatment on at least one of two opposing surfaces of a carrier substrate and a...
US-9,362,158 OTP memory cell and fabricating method thereof
A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and...
US-9,362,157 Method of processing substrate holder material as well as substrate holder processed by such method
A method is provided of processing substrate holder material for a substrate holder on which on a first side of said substrate holder a semiconductor substrate...
US-9,362,156 Dicing tape-integrated film for semiconductor back surface
The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a...
US-9,362,155 Suppporting device, method for manufacturing thin film transistor array substrate and method for manufacturing...
A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface....
US-9,362,154 Method for treatment of a temporarily bonded product wafer
A method for treatment of a product wafer temporarily bonded on a carrier wafer with the following steps: grinding and/or backthinning of the product wafer on...
US-9,362,153 Method for aligning substrates in different spaces and having different sizes
A method for aligning substrates in different spaces and having different sizes includes: capturing actual local images of two substrates; comparing specific...
US-9,362,152 Article supporting device
Each of a pair of support members includes a lightweight-article support portion that is inserted into an insertion space of a lightweight article and supports...
US-9,362,151 Substrate warp correcting device and substrate warp correcting method
A substrate warp correcting device includes, a lower member including a concave portion, and the lower member on which a substrate is to be arranged, an upper...
US-9,362,150 Substrate processing apparatus
A substrate processing apparatus includes a housing, a mounting table provided in the housing and configured to mount a substrate thereon, a drive mechanism...
US-9,362,149 Etching method, etching apparatus, and storage medium
Provided is a method of etching a silicon oxide film, which includes supplying a mixture gas of a halogen element-containing gas and a basicity gas onto a...
US-9,362,148 Shielded lid heater assembly
A shielded lid heater lid heater suitable for use with a plasma processing chamber, a plasma processing chamber having a shielded lid heater and a method for...
US-9,362,147 Substrate treatment method
A substrate treatment method employs a substrate holding unit, a gas ejection nozzle, and a gas supply unit. The substrate holding unit is configured to hold a...
US-9,362,146 Washing device
A washing device is disclosed, which is capable of preventing damage of a substrate caused by drooping of the substrate. The washing device includes a plasma...
US-9,362,145 Semiconductor apparatus and method for producing the same
A method for producing a semiconductor apparatus with a mold including an upper mold half and a lower mold half, includes: an arranging step of arranging on one...
US-9,362,144 Article and panel comprising semiconductor chips, casting mold and methods of producing the same
A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one...
US-9,362,143 Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related...
Methods for forming semiconductor device packages include applying a photoimageable dielectric adhesive material to a major surface of a semiconductor die and...
US-9,362,142 Flip-chip electronic device and production method thereof
A method for making a set of electronic devices is proposed. The method comprises the steps of providing a support comprising a base plate of electrically...
US-9,362,141 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly...
US-9,362,140 Package stack device and fabrication method thereof
A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element, a second package structure...
US-9,362,139 Method of making a semiconductor device having a functional capping
A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising...
US-9,362,138 IC package and method for manufacturing the same
An IC package is provided. The IC package comprises a leadframe comprising a metal strip (222) partially etched on a first side. The leadframe may be configured...
US-9,362,137 Plasma treating apparatus, substrate treating method, and method of manufacturing a semiconductor device
A substrate treating method may be performed by a plasma treating apparatus. The substrate treating method may include: providing a substrate on a platform in a...
US-9,362,136 Method of manufacturing semiconductor device
In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then...
US-9,362,135 Semiconductor device manufacturing method
A semiconductor device manufacturing method, the method including: forming an insulation layer having a protruding portion, the insulation layer having a...
US-9,362,134 Chip package and fabrication method thereof
A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of...
US-9,362,133 Method for forming a mask by etching conformal film on patterned ashable hardmask
Methods and apparatuses for multiple patterning using image reversal are provided. The methods may include depositing gap-fill ashable hardmasks using a...
US-9,362,132 Systems and methods for a sequential spacer scheme
The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second...
US-9,362,131 Fast atomic layer etch process using an electron beam
An etch process gas is provided to a main process chamber having an electron beam plasma source, and during periodic passivation operations a remote plasma...
US-9,362,130 Enhanced etching processes using remote plasma sources
Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate...
US-9,362,129 Polishing apparatus and polishing method
A polishing apparatus is used for polishing a surface of a substrate such as a semiconductor wafer to planarize the surface of the substrate. The polishing...
US-9,362,128 Methods for fabricating integrated circuits and components thereof
Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for a fabricating a...
US-9,362,127 Method for processing a workpiece by forming a pourous metal layer
A method for processing a workpiece may include: providing a workpiece including a first region and a second region; forming a porous metal layer over the first...
US-9,362,126 Process for making a patterned metal oxide structure
There is provided a process for making a patterned metal oxide structure comprising the step of heating an imprint structure comprising a polymerized...
US-9,362,125 Semiconductor process
A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned...
US-9,362,124 Method of patterning a metal gate of semiconductor device
Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide...
US-9,362,123 Structure and method for integrated devices on different substartes with interfacial engineering
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first...
US-9,362,122 Process for contact doping
Provided is a process for modifying the chemical composition of a surface region of a material, employing rapid thermal processing (RTP) conditions.
US-9,362,121 Method of manufacturing a silicon carbide semiconductor device
A silicon carbide substrate including a first impurity region, a well region, and a second impurity region separated from the first impurity region by the well...
US-9,362,120 Lithography process and composition with de-crosslinkable crosslink material
The present disclosure provides a method that includes forming a polymeric material layer on a substrate, wherein the polymeric material layer includes...
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