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Impregnated continuous graphitic fiber tows and composites containing same
An impregnated fiber tow comprising multiple unitary graphene-based continuous graphitic fibers impregnated with a matrix material, wherein at least one of the...
Paste composition for front electrode of solar cell, and solar cell
including the same
Provided is a paste composition for front electrode of a solar cell. The paste composition includes conductive power, an organic vehicle, a glass frit, and an...
Cathode active material, method for making the same and lithium ion
battery using the same
A cathode active material of a lithium ion battery includes a number of LiNi.sub.0.5Mn.sub.1.5O.sub.4 particles and an AlF.sub.3 layer coated on a surface of...
Silicon-based solar cell with eutectic composition
Growth and characterization of low cost, and high efficiency micro- and nanostructured p-n heterojunction solar cells through eutectic solidification are...
Plate-like electric conductor for a busbar and the busbar formed therefrom
A plate-like electric conductor for a busbar having excellent electric conductivity, strength and bendability, and a busbar formed therefrom. The electric...
Tilting collimator, in particular for single-photon emission computed
A tilting collimator (4), in particular usable in the single photon emission computed tomography imaging technique, comprises: a plurality of side-by-side...
Packaging of radioactive waste by cementing
Using crystalline silica, mixed with cement powder, to reduce the heating of the cement paste caused by the hydration of said powder, during a process of...
Nuclear reactor assembly having a connection between a control rod guide
tube and a drive housing pipe
A boiling water reactor assembly includes a bayonet plate closure between a control rod guide tube and a drive housing pipe. The bayonet plate closure has a...
Passive reactivity control apparatus
In response to a change in a thermal operational parameter in a nuclear fission reactor, reactivity is controlled by driving a neutron absorption parameter...
Cross-section reducing isotope system
An isotope production target rod for a power generating nuclear reactor is provided. The isotope production target rod can include at least one rod central body...
Memory device using soft and hard repair operations and memory system
including the same
A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit...
Semiconductor memory device
A data transfer unit includes a first page buffer to latch data of a normal bit line connected to a normal memory cell, a second page buffer to latch data of a...
The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a...
Semiconductor device for parallel bit test and test method thereof
A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory...
Semiconductor device, semiconductor memory device and memory system
A semiconductor device includes a nonvolatile memory block suitable for outputting data stored in a plurality of nonvolatile memory cells included therein based...
System and method to decode data subject to a disturb condition
A method includes initiating a first decode operation of data at an error correction code (ECC) hard bit decoder in a data storage device that includes a...
Stacked semiconductor device
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with...
Memory cell capable of operating under low voltage conditions
A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by...
Memory system and management method thereof
According to one embodiment, a memory system comprises a first nonvolatile semiconductor memory, a temperature sensor and a controller. The first nonvolatile...
Data storage device and error correction method capable of adjusting
The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation...
Semiconductor memory device and data writing method of the same
A semiconductor memory device includes memory cells which are laminated on a semiconductor substrate and include charge storage layers and control gates, a...
Storage devices and methods of operating storage devices
A method of operating a storage device may include receiving a read command and a read address, performing a read operation on selected memory cells...
Inferring threshold voltage distributions associated with memory cells via
Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes...
Flash memory system using complementary voltage supplies
A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the...
Method of increasing read current window in non-volatile memory
A memory structure is provided including an array of non-volatile memory (NVM) cells arranged in rows and columns, each cell including a NVM transistor having a...
Method of reducing hot electron injection type of read disturb in memory
Read disturb is reduced in a charge-trapping memory device such as a 3D memory device by optimizing the channel boosting voltage in an unselected NAND string. A...
Low voltage semiconductor memory device and method of operation
A semiconductor device for storing data includes a memory cell. The memory cell comprises a plurality of transistors. A trimmable sense amplifier is...
Efficient scanning of nonvolatile memory blocks
A method of searching for a boundary between a written portion and an unwritten portion of an open block may include performing a word line by word line binary...
Time domain ramp rate control for erase inhibit in flash memory
When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word...
Memory device and data erasing method thereof
A memory device comprises a first memory string and a second memory string. The first memory string is coupled to a first bit line and a plurality of word...
Semiconductor memory device
A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate...
Managing data writing to memories
Systems and processes may use a first memory, a second memory, and a memory controller. The second memory is at least as large as a block of the first memory....
High endurance non-volatile storage
A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile...
Nonvolatile memory devices including simultaneous impedance calibration
and input command
An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence...
Flash-based memory system with robust backup and restart features and
A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to...
Semiconductor device and method of refresh thereof
The present invention relates to a semiconductor device, including memory blocks suitable for storing data, peripheral circuits suitable for refreshing the...
Embedded non-volatile memory with single polysilicon layer memory cells
programmable through band-to-band...
A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control...
Methods of forming and programming memory devices with isolation
Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a...
RRAM array using multiple reset voltages and method of resetting RRAM
array using multiple reset voltages
According to another embodiment, a method of reset operation for a resistive random access memory (RRAM) array, having a first RRAM connected to a first word...
Apparatuses including cross point memory arrays and biasing schemes
Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row)...
Series connected resistance change memory device
The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by...
Reliable read operation for nonvolatile memory device with resistance
material that reads data based on...
Provided is a nonvolatile memory device. The nonvolatile memory device may include a resistive memory cell, a reference current generator which provides a...
Sense amplifier including a single-transistor amplifier and level shifter
and methods therefor
Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected...
Sensing data in resistive switching memory devices
Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can...
Resistive memory device and method of operating the same to reduce leakage
A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection...
Multi-channel, multi-bank memory with wide data input/output
An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address...
Charge level maintenance in a memory
In one embodiment, a memory such as a dynamic random access memory employs charge boosting to bitcells prior to sensing charge levels in the storage nodes of...
A semiconductor module includes a wiring layer for data signal lines on which all data signal lines transferring a data signal are wired, a wiring layer for...
Configuration for power reduction in DRAM
Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline...
Semiconductor device and method for driving the same
A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature...