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Patent # Description
US-9,361,267 Splitable and scalable normalizer for vector data
A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector...
US-9,361,266 System and method for distributed computing
The invention refers to tightly coupled multiprocessor distributed computing systems. The proposed solution enables to develop distributed applications as usual...
US-9,361,265 Method and device for integrating a device into a network
A method and a server for integrating a device into a network, a first device identification of the device is detected being a reading device authorized for...
US-9,361,264 Systems and methods for access and control of hardware device resources using device-independent access interfaces
Systems and methods are provided that enable seamless access and control of hardware device resources through a common, device-independent interface without the...
US-9,361,263 Co-located clouds, vertically integrated clouds, and federated clouds
A computer implemented method, program product, and apparatus for managing big data clouds comprising co-locating a big data storage cloud with a second big...
US-9,361,262 Redundant storage enclosure processor (SEP) implementation for use in serial attached SCSI (SAS) environment
An information handling system includes a storage enclosure operable to communicate with a storage initiator. The storage enclosure includes a first controller...
US-9,361,261 Device for exchanging data between at least two applications
The present invention relates to devices for exchanging data between at least two data consuming and/or emitting applications A1, A2. The device has two modules...
US-9,361,260 Master device that changes data communication speed when preparation to drive motor is completed
A first communication speed setting unit sets a data communication speed of data transmitted and received between the master device and the slave device during...
US-9,361,259 Integrated circuit with multipurpose processing and for video/audio processing optimization
An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of...
US-9,361,258 Common interface/conditional access module and method of transmitting data between common interface card and...
A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner...
US-9,361,257 Mechanism for facilitating customization of multipurpose interconnect agents at computing devices
A mechanism is described for facilitating customization of multipurpose interconnect agents at computing devices according to one embodiment of the invention. A...
US-9,361,256 SAS expander with non-blocking virtual phy architecture
A SAS expander includes a switch core, a number of SAS expander phys coupled to the switch core, an SMP originator coupled to the switch core and an SMP...
US-9,361,255 Method for controlling I/O switch, method for controlling virtual computer, and computer system
The present invention is provided with: computers provided with a processor, a memory, and an I/O interface; an I/O switch for connecting a plurality of the...
US-9,361,254 Memory device formed with a semiconductor interposer
A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the...
US-9,361,253 Signal control circuit, information processing apparatus, and duty ratio calculation method
A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of...
US-9,361,252 Electronic device having a plurality of CPUs and a method
An electronic device includes a first CPU, a second CPU, an auxiliary storage unit, and a controller. The auxiliary storage unit includes a first starting...
US-9,361,251 Interrupt signal accepting apparatus and computer apparatus managing operations of at least two operating systems
An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an...
US-9,361,250 Memory module and method for exchanging data in memory module
The present application provides a memory module. The memory module includes one or more volatile memory devices, one or more non-volatile memory devices, and a...
US-9,361,249 Communication apparatus, communication system and adapter
A communication apparatus for carrying out communications to and from an external apparatus that includes a first interconnecting unit and a first ...
US-9,361,248 I/O co-processor coupled hybrid computing device
An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at...
US-9,361,247 Intrinsic barrier device with software configurable IO type
An intrinsic barrier device, method and computer program product for isolating a communication channel of an input/output (IO) module from a field device. The...
US-9,361,246 System-on-chip processing secure contents and mobile device comprising the same
A mobile device is provided which includes a working memory having a memory area divided into a secure domain and a non-secure domain; and a system-on-chip...
US-9,361,245 Location sensitive solid state drive
A data storage system including a SSD includes a capability to detect whether its location is acceptable for function, and a capability to self-disable in the...
US-9,361,244 Apparatus for hardware accelerated runtime integrity measurement
Techniques are described for providing processor-based dedicated fixed function hardware to perform runtime integrity measurements for detecting attacks on...
US-9,361,243 Method and system for providing restricted access to a storage medium
A system, apparatus, method, or computer program product of restricting file access is disclosed wherein a set of file write access commands are determined from...
US-9,361,242 Return stack buffer having multiple address slots per stack entry
A return stack buffer (RSB) is modified such that each entry comprises two or more address slots. When a function is called, the address following the function...
US-9,361,241 Grouping tracks for destaging
Tracks are selected for destaging from a least recently used (LRU) list and the selected tracks are moved to a destaging wait list. The selected tracks are...
US-9,361,240 Dynamic reservations in a unified request queue
A unified request queue includes multiple entries for servicing multiple types of requests. Each of the entries of the unified request queue is generally...
US-9,361,239 System on chip including unified input/output memory management unit
A system on chip, includes a memory, a bus, a plurality of intellectual property (IP) blocks, and a unified input/output memory management unit (IOMMU)...
US-9,361,238 Memory addressing mechanism using a buffer of a hierarchy of collision free hash tables
Methods and apparatuses for insertion, searching, deletion, and load balancing using a hierarchical series of hash tables are described herein. The techniques...
US-9,361,237 System and method for exclusive read caching in a virtualized computing environment
A technique for efficient cache management demotes a unit of data from a higher cache level to a lower cache level in a cache hierarchy when the higher level...
US-9,361,236 Handling write requests for a data array
A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address...
US-9,361,235 Information processing apparatus, method of controlling the same and computer-readable storage medium
A cache storage apparatus has an entry including a tag bit for managing an address in the memory of the data, the data, and a reference count for managing a...
US-9,361,234 Utilization of processor capacity at low operating frequencies
In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a...
US-9,361,233 Method and apparatus for shared line unified cache
An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped...
US-9,361,232 Selectively reading data from cache and primary storage
Techniques are provided for using an intermediate cache to provide some of the items involved in a scan operation, while other items involved in the scan...
US-9,361,231 Implicit I/O send on cache operations
A method for implicit input-output send on cache operations of a central processing unit is provided. The method comprises an aggregation queue of a central...
US-9,361,230 Three channel cache-coherency socket protocol
A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information...
US-9,361,229 Distributed shared caching for clustered file systems
Systems and methods for distributed shared caching in a clustered file system, wherein coordination between the distributed caches, their coherency and...
US-9,361,228 Cache line compaction of compressed data segments
Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying,...
US-9,361,227 Systems and methods for faster read after write forwarding using a virtual address
Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from...
US-9,361,226 Adjusting a memory transfer setting with large main memory capacity
An apparatus for adjusting a memory transfer setting includes a storage device storing machine-readable code and a processor executing the machine-readable...
US-9,361,225 Centralized memory allocation with write pointer drift correction
A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a...
US-9,361,224 Non-intrusive storage of garbage collector-specific management data
A system, method, and techniques for managing memory are provided. An example method includes identifying a plurality of regions in a heap storing one or more...
US-9,361,223 Storage method and apparatus for random access memory using codeword storage
A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead...
US-9,361,222 Electronic system with storage drive life estimation mechanism and method of operation thereof
Systems, methods and/or devices are used to enable storage drive life estimation. In one aspect, the method includes (1) determining two or more age criteria of...
US-9,361,221 Write amplification reduction through reliable writes during garbage collection
The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction through reliable writes during...
US-9,361,220 Apparatus and method of using dummy data while storing data at a multi-bit storage element
A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data...
US-9,361,219 Information processing device, information processing method and program product
An information processing device includes a first storage unit configured to store a set value indicating a value corresponding to a set item to define a...
US-9,361,218 Method of allocating referenced memory pages from a free list
Memory pages that are allocated to a memory consumer and continue to be accessed by the memory consumer are included in a free list, so that they may be...
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