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Patent # Description
US-9,368,622 Stitched gate GaN HEMTs
Principles of the present invention reduces the maximum electric field strength between a gate and a source or drain in a FET by breaking up the usually...
US-9,368,621 Power semiconductor device having low on-state resistance
A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination...
US-9,368,620 Trench gate FET with self-aligned source contact
A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and...
US-9,368,619 Method for inducing strain in vertical semiconductor columns
A vertical Metal-Oxide-Semiconductor (MOS) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material....
US-9,368,618 Semiconductor structure
A semiconductor structure comprising an improved ESD protection device is provided. The semiconductor structure comprises a substrate, a well formed in the...
US-9,368,617 Superjunction device and semiconductor structure comprising the same
The present disclosure relates to a superjunction device and a semiconductor structure having the same. The superjunction device includes a body region of a...
US-9,368,616 Semiconductor device
The semiconductor device includes: a semiconductor layer in which a trench is formed having a side surface and a bottom surface; a second conductivity-type...
US-9,368,615 Trench power field effect transistor device and method
In one embodiment, a structure for a trench power field effect transistor device with controlled, shallow, abrupt, body contact regions.
US-9,368,614 Flexibly scalable charge balanced vertical semiconductor power devices with a super-junction structure
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches....
US-9,368,613 Semiconductor device and method for manufacturing semiconductor device
A protective diode has a basic structure including an n.sup.+ layer, an n.sup.- layer, a p.sup.+ layer, and an n.sup.- layer in this order. A p-type layer...
US-9,368,612 Semiconductor device with diode trench and schottky electrode
Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A...
US-9,368,611 Integrated circuit comprising a MOS transistor having a sigmoid response and corresponding method of fabrication
An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source...
US-9,368,610 High electron mobility transistor with indium nitride layer
A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The...
US-9,368,609 Semiconductor device including a trench with a corner having plural tapered portions
A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the...
US-9,368,608 Heterojunction bipolar transistor with improved performance and breakdown voltage
Fabrication methods for a device structure and device structures. A trench isolation region is formed that bounds an active device region of a semiconductor...
US-9,368,607 Semiconductor device
To provide a semiconductor device having a structure capable of suppressing deterioration of its electrical characteristics which becomes apparent with...
US-9,368,606 Memory first process flow and device
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate...
US-9,368,605 Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and...
A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a...
US-9,368,604 Method of removing threading dislocation defect from a fin feature of III-V group semiconductor material
The present disclosure provides a method of forming a fin-like field-effect transistor (FinFET) device. The method includes forming a first strain-relaxed...
US-9,368,603 Contact for high-k metal gate device
An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving...
US-9,368,602 Method for fabricating IGZO layer and TFT
Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps:...
US-9,368,601 Method for forming oxide below control gate in vertical channel thin film transistor
A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and...
US-9,368,600 Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of trenches in a semiconductor substrate, on opposite...
US-9,368,599 Graphene/nanostructure FET with self-aligned contact and gate
A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a...
US-9,368,598 Method of manufacturing a semiconductor device that includes a MISFET
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The...
US-9,368,597 Semiconductor devices and methods of manufacturing the same
Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The methods may include forming a sacrificial gate pattern on a...
US-9,368,596 Structure and method for a field effect transistor
Provided is one embodiment of a semiconductor structure that includes a STI feature, wherein the STI feature is a continuous feature and includes a first...
US-9,368,595 Semiconductor device provided with an IE type trench IGBT
A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell...
US-9,368,594 Method of forming a fin-like BJT
A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided....
US-9,368,593 Multiple thickness gate dielectrics for replacement gate field effect transistors
After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on...
US-9,368,592 Metal gate structure
The present disclosure provides a semiconductor structure, including a substrate, a metal gate, a dielectric layer, and an etch stop layer. The metal gate is...
US-9,368,591 Transistors comprising doped region-gap-doped region structures and methods of fabrication
Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of...
US-9,368,590 Silicon-on-insulator transistor with self-aligned borderless source/drain contacts
A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a...
US-9,368,589 Semiconductor device and semiconductor module
A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a...
US-9,368,588 Integrated circuits with non-volatile memory and methods for manufacture
Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device...
US-9,368,587 Accumulation-mode field effect transistor with improved current capability
An accumulation-mode field effect transistor including a plurality of gates. The accumulation-mode field effect transistor including a semiconductor region...
US-9,368,586 Transistor with recess gate and method for fabricating the same
A transistor including a recessed gate structure having improved doping characteristics and a method for forming such a transistor. The transistor includes a...
US-9,368,585 Arrangement and method for manufacturing a crystal from a melt of a raw material and single crystal
An arrangement for manufacturing a crystal of the melt of a raw material comprises: a furnace having a heating device with one or more heating elements, which...
US-9,368,584 Gallium nitride power semiconductor device having a vertical structure
A semiconductor device includes a substrate having first and second sides and a first active layer disposed over the first side of the substrate. A second...
US-9,368,583 Field effect transistor with narrow bandgap source and drain regions and method of fabrication
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer...
US-9,368,582 High power gallium nitride electronics using miscut substrates
An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the...
US-9,368,581 Integrated circuitry components, switches, and memory cells
A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair....
US-9,368,580 Semiconductor material doping
A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the...
US-9,368,579 Selective area growth of germanium and silicon-germanium in silicon waveguides for on-chip optical interconnect...
A robust fabrication process for selective area growth of semiconductors in growth windows is provided. Sidewall growth is eliminated by the presence of a...
US-9,368,578 Methods of forming substrates comprised of different semiconductor materials and the resulting device
Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and...
US-9,368,577 Semiconductor device and method for producing semiconductor device
Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n.sup.- drift layer, forming an n-type...
US-9,368,576 Methods of manufacturing trench semiconductor devices with edge termination structures
Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an...
US-9,368,575 Semiconductor device having super junction structure and method for manufacturing the same
A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns...
US-9,368,574 Nanowire field effect transistor with inner and outer gates
A semiconductor device comprising a suspended semiconductor nanowire inner gate and outer gate. A first epitaxial dielectric layer surrounds a nanowire inner...
US-9,368,573 Methods for manufacturing a semiconductor device
In various embodiments, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include forming a...
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