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Patent # Description
US-9,368,521 TFT substrate
A TFT substrate (100) includes a gate line (2) and a source line (4), a TFT (6), a transparent pixel electrode (30) electrically coupled with the TFT, a...
US-9,368,520 Array substrate, manufacturing method thereof and display device
The present invention provides array substrate, manufacturing method thereof, and display device, relating to manufacturing technology field of liquid crystal...
US-9,368,519 Semiconductor device and electronic appliance
The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of...
US-9,368,518 Thin film transistor array panel and method for manufacturing the same
A thin film transistor array panel includes: a gate conductor disposed on a substrate and including a gate line and a gate electrode, a semiconductor layer...
US-9,368,517 Semiconductor device including bonding portion with first and second sealing materials
A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a...
US-9,368,516 Display device and electronic appliance
A display device with low manufacturing cost, a display device with low power consumption, a display device capable of being formed over a large substrate, a...
US-9,368,515 Thin film transistor array panel and method of manufacturing the same
A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed...
US-9,368,514 Semiconductor device and manufacturing method thereof
[Problem] A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high....
US-9,368,513 Highly conformal extension doping in advanced multi-gate devices
A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor...
US-9,368,512 Double diamond shaped unmerged epitaxy for tall fins in tight pitch
A semiconductor structure is provided that includes a semiconductor fin extending upwards from a surface of a substrate. A source/drain structure is located on...
US-9,368,511 Three-dimensional (3D) semiconductor device
A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics,...
US-9,368,510 Method of forming memory cell with high-k charge trapping layer
A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage...
US-9,368,509 Three-dimensional memory structure having self-aligned drain regions and methods of making thereof
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying...
US-9,368,508 Memory device
There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one...
US-9,368,507 Semiconductor structure
A semiconductor device comprises a plurality of stacking blocks and a plurality of conductive lines. Each stacking blocks comprises two opposite finger VG...
US-9,368,506 Integrated circuits and methods for operating integrated circuits with non-volatile memory
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor...
US-9,368,505 Read-only memory and its manufacturing method
A read-only memory includes a plurality of storage units arranged in an array. The read-only memory includes two kinds of storage units with different...
US-9,368,504 Semiconductor device and manufacturing method thereof
Variations in the contact area between contact plugs are suppressed to suppress fluctuations in contact resistance. In three third interlayer insulating films,...
US-9,368,503 Semiconductor SRAM structures
Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an...
US-9,368,502 Replacement gate multigate transistor for embedded DRAM
A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire...
US-9,368,501 Semiconductor memory device including stacked sub memory cells
A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line,...
US-9,368,500 Complementary metal-oxide-semiconductor device
A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating...
US-9,368,499 Method of forming different voltage devices with high-k metal gate
A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with...
US-9,368,498 FinFET device with dual-strained channels and method for manufacturing thereof
A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures....
US-9,368,497 Fin field-effect transistors and fabrication method thereof
A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the...
US-9,368,496 Method for uniform recess depth and fill in single diffusion break for fin-type process and resulting devices
Methods for creating uniform source/drain cavities filled with uniform levels of materials in an IC device and resulting devices are disclosed. Embodiments...
US-9,368,495 Semiconductor devices having bridge layer and methods of manufacturing the same
A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on...
US-9,368,494 Semiconductor device and method of manufacturing the same
A semiconductor device with neck fins comprises a substrate, a plurality of fins having a lower portion and a neck upper portion on the substrate, and...
US-9,368,493 Method and structure to suppress FinFET heating
Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A...
US-9,368,492 Forming fins of different materials on the same substrate
A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried...
US-9,368,491 Enhancement mode inverter with variable thickness dielectric stack
An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first...
US-9,368,490 Enhancement-depletion mode inverter with two transistor architectures
An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a...
US-9,368,489 Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One...
US-9,368,488 Efficient integration of CMOS with poly resistor
Device and methods for forming a device are presented. The method includes providing a substrate. The substrate includes a resistor region defined by a resistor...
US-9,368,487 Semiconductor device with dynamic low voltage triggering mechanism
An electrostatic discharge (ESD) protection device is disclosed, which includes a substrate of a positive dopant type; a p-well defined in the substrate; a...
US-9,368,486 Direct connected silicon controlled rectifier (SCR) having internal trigger
In one aspect, a direct connected silicon control rectifier (DCSCR) includes a substrate having a semiconductor surface, a parasitic PNP bipolar transistor and...
US-9,368,485 Electrostatic discharge circuitry with separate power rails
In one embodiment, an integrated circuit includes an input-output circuit, first and second electrostatic discharge diode circuits, first and second power clamp...
US-9,368,484 Fin type electrostatic discharge protection device
A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a...
US-9,368,483 Illumination device capable of decreasing shadow of lighting effect
A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a...
US-9,368,482 Stack packages and methods of fabricating the same
Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first...
US-9,368,481 Semiconductor devices and packages having through electrodes
A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes...
US-9,368,480 Semiconductor device and method of manufacturing semiconductor device
Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate...
US-9,368,479 Thermal vias disposed in a substrate proximate to a well thereof
An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at...
US-9,368,478 Microelectronic package and method of manufacture thereof
A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening...
US-9,368,477 Co-support circuit panel and microelectronic packages
A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic...
US-9,368,476 Stacked microelectronic assembly with TSVs formed in stages with plural active chips
A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic...
US-9,368,475 Semiconductor device and manufacturing method thereof
A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in...
US-9,368,474 Manufacturing method for semiconductor device
A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein;...
US-9,368,473 Assembly method, of the flip-chip type, for connecting two electronic components, assembly obtained by the method
The invention relates to an assembly method for connecting two electronic components together, said components each having an assembly face, wherein the two...
US-9,368,472 Flip-chip assembly process for connecting two components to each other
The invention relates to a flip-chip assembly process for connecting two microelectronic components (1, 2) to each other. According to the invention, it is...
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