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Patent # Description
US-9,368,471 Wire-bonding apparatus and method of manufacturing semiconductor device
Provided is a wire-bonding apparatus (10) including: a capillary (28) through which a wire (30) is inserted; a nonsticking determination circuit (36) configured...
US-9,368,470 Coated bonding wire and methods for bonding using same
A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating over...
US-9,368,469 Electronic component package and method of manufacturing same
There is provided a method for manufacturing an electronic component package. The method includes the steps: (i) disposing a metal pattern layer on an adhesive...
US-9,368,468 Thin integrated circuit chip-on-board assembly
An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating...
US-9,368,467 Substrate structure and semiconductor package using the same
A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an...
US-9,368,466 Bump I/O contact for semiconductor device
A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an...
US-9,368,465 Method of forming bump pad structure having buffer pattern
The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center...
US-9,368,464 Electronic component, mother substrate, and electronic component manufacturing method
An electronic component includes a plurality of electrodes provided in a rectangular or substantially rectangular box-shaped area on an upper surface of a...
US-9,368,463 Semiconductor device
Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the...
US-9,368,462 Methods and apparatus of packaging semiconductor devices
Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by...
US-9,368,461 Contact pads for integrated circuit packages
Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a...
US-9,368,460 Fan-out interconnect structure and method for forming same
A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached...
US-9,368,459 Semiconductor chip with seal ring and sacrificial corner pattern
A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal...
US-9,368,458 Die-on-interposer assembly with dam structure and method of manufacturing the same
A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a...
US-9,368,457 High-frequency package
A high-frequency package includes an MMIC including a signal source and a conductor pattern that is connected to the signal source, a substrate having a signal...
US-9,368,456 Semiconductor package having EMI shielding and method of fabricating the same
A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer,...
US-9,368,455 Electromagnetic interference shield for semiconductor chip packages
An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a package has a semiconductor die. a redistribution...
US-9,368,454 Semiconductor device with shielding layer in post-passivation interconnect structure
A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI)...
US-9,368,453 Overlay mark dependent dummy fill to mitigate gate height variation
A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting...
US-9,368,452 Metal conductor chemical mechanical polish
The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical...
US-9,368,451 Multichip module with reroutable inter-die communication
A multichip module (MCM) has redundant I/O connections between its dice. That is, the number of inter-die I/O connections used is larger than the number of...
US-9,368,450 Integrated device package comprising bridge in litho-etchable layer
An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution...
US-9,368,448 Metal-containing films as dielectric capping barrier for advanced interconnects
A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a...
US-9,368,447 Electronic device and method for production
An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or...
US-9,368,446 Self aligned contact formation
The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate...
US-9,368,445 E-fuse structure of semiconductor device
Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode...
US-9,368,444 Self-aligned nano-structures
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer...
US-9,368,443 Memory metal scheme
A memory includes a plurality of memory cells. A first line is over the plurality of memory cells. The first line in a first layout section includes a first...
US-9,368,442 Method for manufacturing an interposer, interposer and chip package structure
A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each...
US-9,368,441 Electronic component and method for fabricating the same
An electronic component and a method for fabricating the electronic component are provided. The electronic component includes a carrier, a first metal layer, a...
US-9,368,440 Embedded coaxial wire and method of manufacture
A method of manufacturing an integrated circuit package substrate is disclosed. The method may include forming a hole through a substrate layer in the package...
US-9,368,439 Substrate build up layer to achieve both finer design rule and better package coplanarity
Embodiments of the invention generally relate to package substrates for integrated circuits. The package substrates each include a core having electrically...
US-9,368,438 Package on package (PoP) bonding structures
Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on...
US-9,368,437 High density package interconnects
Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die...
US-9,368,436 Source down semiconductor devices and methods of formation thereof
A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device...
US-9,368,435 Electronic component
In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive...
US-9,368,434 Electronic component
In an embodiment, an electronic component includes a housing, a die pad having a first surface and a second surface opposing the first surface, a first high...
US-9,368,433 Method and apparatus for mounting solder balls to an exposed pad or terminal of a semiconductor package
Embodiments of the present disclosure provide a package comprising a die attach pad, a die disposed on the die attach pad and a leadframe. The leadframe...
US-9,368,432 Semiconductor device and manufacturing method of semiconductor device
A technique capable of enhancing a reliability of a semiconductor device is provided. A semiconductor device has a die pad on which a semiconductor chip is...
US-9,368,431 Semiconductor apparatus
A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance...
US-9,368,430 Semiconductor device and semiconductor device fabrication method
A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating...
US-9,368,429 Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an...
US-9,368,428 Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
A method for fabricating semiconductor and electronic devices at the wafer level is described. In this method, dielectric material is used to wafer bond a...
US-9,368,427 Integrated circuit film and method of manufacturing the same
An integrated circuit film and a method of manufacturing the same are disclosed. The integrated circuit film includes a circuit board containing a circuit...
US-9,368,426 Piezoelectric fan and air cooling apparatus using the piezoelectric fan
A piezoelectric fan includes a vibration plate one end of which in a length direction is supported in a fixed manner and the other end of which in the length...
US-9,368,425 Embedded heat spreader with electrical properties
Embodiments of the invention relate to incorporating one or more antennas or inductor coils into a semi-conductor package. A heat spreader or metal sheet is...
US-9,368,424 Method of fabricating a semiconductor device used in a stacked-type semiconductor device
A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals...
US-9,368,423 Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded...
A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. A semiconductor die is disposed on a...
US-9,368,422 Absorbing excess under-fill flow with a solder trench
One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill...
US-9,368,421 Under-fill material and method for producing semiconductor device
The present invention provides an under-fill material with which a semiconductor device having a high connection reliability can be provided while securing a...
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