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Patent # Description
US-9,368,420 Flexible, stretchable electronic devices
Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g....
US-9,368,418 Copper wiring structure forming method
In a Cu wiring structure forming method, a barrier film serving as a Cu diffusion barrier is formed at least on a surface of a recess in a first insulating film...
US-9,368,417 Contact test structure and method
A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with...
US-9,368,416 Continuous voltage product binning
A binning process uses curve fitting to create and assign one or more bins based on testing data of operating voltage versus leakage current for test integrated...
US-9,368,415 Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers
A semiconductor material stack of, from bottom to top, a first semiconductor material having a first lattice constant and a second semiconductor material having...
US-9,368,414 Semiconductor inspecting apparatus and method of inspecting and manufacturing semiconductor device using the same
A method of manufacturing a semiconductor device includes: preparing a semiconductor device comprising a first substrate, a second substrate disposed on the...
US-9,368,413 Light exposure condition analysis method, nontransitory computer readable medium storing a light exposure...
According to one embodiment, a pattern formed through light exposure is observed under two or more different optical conditions, and a focus shift and exposure...
US-9,368,412 Method for manufacturing semiconductor device
A method for manufacturing one or more semiconductor devices may include the following steps: providing a dielectric layer on a substrate structure that...
US-9,368,411 Method for the formation of fin structures for FinFET devices
A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the...
US-9,368,410 Semiconductor devices having tensile and/or compressive stress and methods of manufacturing
A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at...
US-9,368,409 Semiconductor structure and fabrication method
The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the...
US-9,368,408 Method of manufacturing a semiconductor device with buried channel/body zone and semiconductor device
A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a...
US-9,368,407 Crack control for substrate separation
A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The...
US-9,368,406 Method for manufacturing semiconductor chip
A method for manufacturing a semiconductor chip includes forming a front-side groove in a front surface of a substrate; forming a back-side groove wider than...
US-9,368,405 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the...
US-9,368,404 Method for dicing a substrate with back metal
The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a...
US-9,368,403 Method for manufacturing a semiconductor device
The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first...
US-9,368,402 Conductive line system and process
A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each...
US-9,368,401 Embedded structures for package-on-package architecture
Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer...
US-9,368,400 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically...
A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive...
US-9,368,399 Semiconductor device and method for forming the same
A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active...
US-9,368,398 Interconnect structure and method of fabricating same
An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed...
US-9,368,397 Method for forming a vertical electrical connection in a layered semiconductor structure
The invention proposes a method for forming a vertical electrical connection (50) in a layered semiconductor structure (1), comprising the following steps:...
US-9,368,396 Gap fill treatment for via process
A gap fill treatment for via process is provided. A substrate with a plurality of openings has formed therein is provided. The substrate includes a dense...
US-9,368,395 Self-aligned via and air gap
Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a...
US-9,368,394 Dry etching gas and method of manufacturing semiconductor device
The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate; forming a conductive...
US-9,368,393 Line-edge roughness improvement for small pitches
A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with...
US-9,368,392 MIM capacitor structure
The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor...
US-9,368,391 CMOS inverters and fabrication methods thereof
A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first...
US-9,368,390 Semiconductor apparatus
A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon...
US-9,368,389 Semiconductor device with voids within silicon-on-insulator (SOI) structure and method of forming the...
A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed...
US-9,368,388 Apparatus for FinFETs
A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped...
US-9,368,387 Method of forming shallow trench isolation structure
A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming...
US-9,368,386 Corner transistor suppression
The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K...
US-9,368,385 Manufacturing method for semiconductor integrated circuit device
A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type...
US-9,368,384 Substrate conveying method, recording medium in which program is recorded for causing substrate conveying...
A substrate conveying method conveying a layered body having first and second substrates stacked with a spacer member provided between their respective bottom...
US-9,368,383 Substrate treating apparatus with substrate reordering
A treating section has substrate treatment lines arranged one over the other for treating substrates while transporting the substrates substantially...
US-9,368,382 Elevator-based tool loading and buffering system
A substrate processing apparatus is provided. The apparatus has a casing, a low port interface and a carrier holding station. The casing has processing devices...
US-9,368,381 Transfer robot, its substrate transfer method and substrate transfer relay device
A transfer robot is equipped with a first hand and a second hand. The first and the second hands, each have two blades, for holding respective substrates. In...
US-9,368,380 Substrate processing device with connection space
Provided is a substrate processing apparatus. The substrate processing apparatus includes a chamber providing a stacking space in which a substrate is stacked...
US-9,368,379 Systems and methods of controlling semiconductor wafer fabrication processes
A system and method of controlling a semiconductor wafer fabrication process. The method includes positioning a semiconductor wafer on a wafer support assembly...
US-9,368,378 Semiconductor wafer cleaning system
A semiconductor wafer cleaning apparatus comprising a first supporting unit, a movable unit having a first chamber, a second supporting unit having a second...
US-9,368,377 Plasma processing apparatus
The present invention provides a temperature control unit for an electrostatic adsorption electrode that is capable of controlling the wafer temperature rapidly...
US-9,368,376 Mechanical debonding method and system
A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer...
US-9,368,375 Apparatus and method for self-aligning chip placement and leveling
An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first...
US-9,368,374 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device is provided. The method includes placing a semiconductor chip by flip-chip mounting on a substrate by using an...
US-9,368,373 Method of joining semiconductor substrate
A method of joining semiconductor substrates includes: forming an alignment key on a first semiconductor substrate; forming a first protrusion and a second...
US-9,368,372 Method for manufacturing semiconductor device
It includes the step of pressing a correcting tool against the main surface of a semiconductor chip while a solder material coated over a die pad is in a molten...
US-9,368,371 Retaining ring having inner surfaces with facets
A retaining ring comprises a generally annular body. The body comprises a top surface, a bottom surface, an outer surface connected to the top surface at an...
US-9,368,370 Temperature ramping using gas distribution plate heat
A method for etching a dielectric layer disposed on a substrate is provided. The method includes de-chucking the substrate from an electrostatic chuck in an...
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