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Fast secure erase in a flash system
A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a...
Voltage generator, integrated circuit, and voltage generating method
A voltage generator includes: a first pump configured to generate and output a first voltage to a first node in response to a first clock signal; a second pump...
Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
Method for biasing an embedded source plane of a non-volatile memory
having vertical select gates
A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a...
Programmable peak-current control in non-volatile memory devices
A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of...
Nonvolatile semiconductor memory device with block decoder
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has...
Memory with temperature coefficient trimming
A device includes an array of memory cells, a temperature sensor to provide a temperature output, and a circuit. The circuit provides a bias voltage to bias a...
Semiconductor memory device having a memory string that includes a
transistor having a charge stored therein to...
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a...
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit....
Embedded non-volatile memory with single polysilicon layer memory cells
programmable through channel hot...
A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an...
Non-volatile latch using magneto-electric and ferro-electric tunnel
A non-volatile memory circuit includes an SRAM cell with magnetoelectric or ferroelectric structures for maintaining data within the SRAM cell even with power...
Method of operating FET low current 3D re-ram
Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a...
Capacitor arrangements using a resistive switching memory cell structure
In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of...
Set and reset operation in phase change memory and associated techniques
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an...
Volatile/non-volatile memory cell
The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a...
Memory device and driving method thereof
A memory device includes a memory array, a word line driver, and source drivers. The memory array includes memory units. The memory units arranged in the same...
Apparatuses, sense circuits, and methods for compensating for a wordline
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a...
Nonvolatile memory device having resistive memory cell and method sensing
data in same
A method of sensing multi-bit data stored in a resistive memory cell includes; determining a resistive value range for the memory cell by performing a first...
Low read current architecture for memory
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage...
A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory...
Circuits and methods for placing programmable impedance memory elements in
high impedance states
A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor...
A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store...
Semiconductor memory device
A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current...
Memory system for processing data from memory device, and method of
operating the same
A memory system includes a memory device including memory blocks, each of the memory blocks including pages, each of the pages including memory cells that are...
Semiconductor integrated circuit device and system with memory cell array
A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated...
Methods for reducing power dissipation in drowsy caches and for retaining
data in cache-memory sleep mode
A method for refreshing static random access memory comprises providing at least one six-transistor static random access memory cell disposed on a substrate and...
Semiconductor device and method for driving the same
A semiconductor device includes a voltage supply unit suitable for providing a first voltage as a source voltage during a standby mode, and a second voltage as...
Time division multiplexing sense amplifier
A circuit comprises a plurality of memory cells, a word line, a plurality of pairs of bit lines, a pre-charge and equalization device, a column select device,...
Semiconductor device including output circuit constituted of plural unit
buffer circuits in which impedance...
A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit...
Semiconductor device performing refresh operation
Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first...
Insertion-override counter to support multiple memory refresh rates
A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh...
A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data...
Memory refresh methods, memory section control circuits, and apparatuses
Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a...
Method for forming an integrated circuit package
An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the...
Nonvolatile storage with long memory endurance having the advantages of easy manufacturability is obtained by using a memory cell having an information storage...
Circuit and method for accessing a bit cell in a spin-torque MRAM
Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces...
Variable resistance memory device and storage devices using the same
In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a...
Magnetic field sensing using magnetoresistive random access memory (MRAM)
A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a...
Resistive memory device, memory system including the same and method of
reading data from the same
A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The...
Magnetic resistance structure, method of manufacturing the magnetic
resistance structure, and electronic device...
Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic...
Scalable magnetoresistive element
One embodiment of a magnetoresistive element comprises: a free ferromagnetic layer comprising a reversible magnetization direction directed substantially...
Semiconductor memory device receiving multiple commands simultaneously and
memory system including the same
A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and...
Data strobe control device
A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first...
Semiconductor memory device
A circuit of a semiconductor memory device may include a delay unit suitable for delaying a column pulse signal, and sequentially generating a first strobe...
Read strobe gating mechanism
A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory...
Semiconductor memory apparatus
A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data...
Memory device with resistance-change type storage elements
According to one embodiment, a memory device includes memory cells including storage elements, each storing information based on a change of resistance, word...
Hardware chip select training for memory using write leveling mechanism
A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a...
Nonvolatile memory device including a peripheral circuit to receive an
address in synch with one of a rising...
A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an...
Semiconductor apparatus and testing method thereof
A semiconductor apparatus having a through via to be electrically coupled with a chip includes a latch memory cell configured to be electrically coupled with...