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Configurable multi-lane scrambler for flexible protocol support
Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of...
Interface configuration for a memory card and memory card control device
Card detection pin and input pin configured to receive an interface reset signal are connected to each other in a high-speed data transfer memory card. A memory...
An expansion card includes a peripheral component interconnect express (PCIe) slot, a PCI expansion controller, a PCIe/serial advanced technology attachment...
Executive device and control method and electronic system thereof
A stack method for executive devices includes the following steps: a present master-slave setting is detected of each execution device, such that the execution...
One or more systems, devices, methods, and/or processes described can receive, via an interconnect, messages from processing nodes, and a first portion of the...
One or more systems, devices, methods, and/or processes described can receive, via an interconnect, messages from processing nodes and a first portion of the...
Electronic device with card interface
When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode...
Communication methods and apparatus and power supply controllers using the
Communication methods and apparatus and power supply controllers using the same. The method includes transferring information over a line from a first location...
Dynamic streaming data dispatcher
A method includes receiving, by a computing device, a plurality of data streams from plurality of sources, distributing the data streams to a plurality of sinks...
Apparatus for multiple bus master engines to share the same request
channel to a pipelined backbone
In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined...
System on chip for enhancing quality of service and method of controlling
A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The...
Resource request arbitration device, resource request arbitration system,
resource request arbitration method,...
A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource...
Reconfigurably designating master core for conditional output on sideband
communication wires distinct from...
A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires,...
DMA transfer device and method
To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with...
High speed integrated circuit interface
A method and apparatus for interfacing integrated circuit chips is disclosed. In one embodiment, the interface includes a set of differential data lines over...
Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
Method and system of communicating between peer processors in SoC
A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a...
Storage virtualization apparatus causing access request process to be
delayed based on incomplete count and...
A storage virtualization apparatus includes: a first storing unit to store, with respect to each storage port, a process incomplete command count defined as...
Method and apparatus for on-the-fly learning traffic control scheme
The present invention discloses a method of arbitrating among a plurality of channels to access a resource, comprising the steps of: providing each channel an...
Reversible connector for accessory devices
Reversible connectors for accessory devices are described. In one or more implementations, a connector cable for an accessory of a host computing device is...
Adjusting the size of a media presentation received by a mobile device
A method, system, and medium are provided for changing the size of media content sent to a mobile device during a media session. In one embodiment, during the...
System on a chip (SoC) RHBD structured ASIC
This invention relates to both a method and device for booting up a device and online scrubbing utilizing a system on chip applique sensor interface module in a...
Mitigating main crossbar load using dedicated connections for certain
One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to...
Extended utilization area for a memory device
Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a...
Storage device, data processing device, registration method, and recording
A storage device includes a switching unit which switches an access destination in a storage area between a first storage area and a second storage area in...
System and apparatus for controlling use of mass storage devices
Disclosed is a software program, USB monitoring software agent. USB monitoring software agent is a software program that monitors all USB ports of a computer...
Acoustically secure phase change memory devices
Systems, methods, and firmware for operating data storage devices and storage processors are provided herein. In one example, a data storage device is provided....
Systems and methods to extend ROM functionality
Various embodiments allow for flexible and secure updates of drivers for numerous types of external memory devices by utilizing an address-selection mechanism...
System and method for updating data in a cache
In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write...
Management of destage tasks with large number of ranks
A processor, operable in a computing storage environment, for each rank in a storage management device in the computing storage environment, allocates a lower...
Controlling direct memory access page mappings
A method for controlling access to a memory of a computer system configured with at least one logical partition may include receiving a first request to map a...
Instruction and logic for support of code modification in translation
A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory...
Memory management apparatus, method, and system
The present invention discloses a memory management apparatus, method, and system. An OS-based memory management apparatus associated with main memory includes...
System and method for cache access
The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache...
Translating cache hints
Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a...
System and method for removing data from processor caches in a distributed
multi-processor computer system
A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor...
Observation of data in persistent memory
Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block...
Fetch width predictor
Various techniques for predicting instruction fetch widths. In one embodiment, a fetch prediction unit in a processor is configured to generate a fetch width...
Bounded cache searches
Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the...
Storage system and cache control method
A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple...
Data cache way prediction
In a particular embodiment, a method includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively...
System and method for managing cache replacements
A system and method for managing cache replacements and a memory subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a...
A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a...
Method and system for improving memory access performance
The present invention relates to a computing system which includes a processor and a memory. It also includes a memory access optimizer which is arranged to...
Cache circuit having a tag array with smaller latency than a data array
A method is described that includes alternating cache requests sent to a tag array between data requests and dataless requests.
System and method utilizing a shared cache to provide zero copy memory
Methods and systems for providing a plurality of applications with concurrent access to data are disclosed. One such method includes identifying attributes of...
Shared memories for energy efficient multi-core processors
Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a...
Ordering constraint management within coherent memory systems
A data processing system including multiple processors 6, 8, 10, 12 each with a local cache memory 14, 16, 18, 20 share a main memory 24 under control of a...
Implicit I/O send on cache operations
A computer system for implicit input-output send on cache operations of a central processing unit is provided. The computer system comprises an aggregation...
Scheduling method and multi-core processor system
A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when...