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Patent # Description
US-9,367,509 Configurable multi-lane scrambler for flexible protocol support
Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of...
US-9,367,508 Interface configuration for a memory card and memory card control device
Card detection pin and input pin configured to receive an interface reset signal are connected to each other in a high-speed data transfer memory card. A memory...
US-9,367,507 Expansion card
An expansion card includes a peripheral component interconnect express (PCIe) slot, a PCI expansion controller, a PCIe/serial advanced technology attachment...
US-9,367,506 Executive device and control method and electronic system thereof
A stack method for executive devices includes the following steps: a present master-slave setting is detected of each execution device, such that the execution...
US-9,367,505 Coherency overcommit
One or more systems, devices, methods, and/or processes described can receive, via an interconnect, messages from processing nodes, and a first portion of the...
US-9,367,504 Coherency overcommit
One or more systems, devices, methods, and/or processes described can receive, via an interconnect, messages from processing nodes and a first portion of the...
US-9,367,503 Electronic device with card interface
When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode...
US-9,367,502 Communication methods and apparatus and power supply controllers using the same
Communication methods and apparatus and power supply controllers using the same. The method includes transferring information over a line from a first location...
US-9,367,501 Dynamic streaming data dispatcher
A method includes receiving, by a computing device, a plurality of data streams from plurality of sources, distributing the data streams to a plurality of sinks...
US-9,367,500 Apparatus for multiple bus master engines to share the same request channel to a pipelined backbone
In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined...
US-9,367,499 System on chip for enhancing quality of service and method of controlling the same
A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The...
US-9,367,498 Resource request arbitration device, resource request arbitration system, resource request arbitration method,...
A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource...
US-9,367,497 Reconfigurably designating master core for conditional output on sideband communication wires distinct from...
A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires,...
US-9,367,496 DMA transfer device and method
To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with...
US-9,367,495 High speed integrated circuit interface
A method and apparatus for interfacing integrated circuit chips is disclosed. In one embodiment, the interface includes a set of differential data lines over...
US-9,367,494 Data processor and control system
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
US-9,367,493 Method and system of communicating between peer processors in SoC environment
A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a...
US-9,367,492 Storage virtualization apparatus causing access request process to be delayed based on incomplete count and...
A storage virtualization apparatus includes: a first storing unit to store, with respect to each storage port, a process incomplete command count defined as...
US-9,367,491 Method and apparatus for on-the-fly learning traffic control scheme
The present invention discloses a method of arbitrating among a plurality of channels to access a resource, comprising the steps of: providing each channel an...
US-9,367,490 Reversible connector for accessory devices
Reversible connectors for accessory devices are described. In one or more implementations, a connector cable for an accessory of a host computing device is...
US-9,367,489 Adjusting the size of a media presentation received by a mobile device
A method, system, and medium are provided for changing the size of media content sent to a mobile device during a media session. In one embodiment, during the...
US-9,367,488 System on a chip (SoC) RHBD structured ASIC
This invention relates to both a method and device for booting up a device and online scrubbing utilizing a system on chip applique sensor interface module in a...
US-9,367,487 Mitigating main crossbar load using dedicated connections for certain traffic types
One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to...
US-9,367,486 Extended utilization area for a memory device
Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a...
US-9,367,485 Storage device, data processing device, registration method, and recording medium
A storage device includes a switching unit which switches an access destination in a storage area between a first storage area and a second storage area in...
US-9,367,484 System and apparatus for controlling use of mass storage devices
Disclosed is a software program, USB monitoring software agent. USB monitoring software agent is a software program that monitors all USB ports of a computer...
US-9,367,483 Acoustically secure phase change memory devices
Systems, methods, and firmware for operating data storage devices and storage processors are provided herein. In one example, a data storage device is provided....
US-9,367,482 Systems and methods to extend ROM functionality
Various embodiments allow for flexible and secure updates of drivers for numerous types of external memory devices by utilizing an address-selection mechanism...
US-9,367,480 System and method for updating data in a cache
In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write...
US-9,367,479 Management of destage tasks with large number of ranks
A processor, operable in a computing storage environment, for each rank in a storage management device in the computing storage environment, allocates a lower...
US-9,367,478 Controlling direct memory access page mappings
A method for controlling access to a memory of a computer system configured with at least one logical partition may include receiving a first request to map a...
US-9,367,477 Instruction and logic for support of code modification in translation lookaside buffers
A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory...
US-9,367,476 Memory management apparatus, method, and system
The present invention discloses a memory management apparatus, method, and system. An OS-based memory management apparatus associated with main memory includes...
US-9,367,475 System and method for cache access
The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache...
US-9,367,474 Translating cache hints
Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a...
US-9,367,473 System and method for removing data from processor caches in a distributed multi-processor computer system
A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor...
US-9,367,472 Observation of data in persistent memory
Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block...
US-9,367,471 Fetch width predictor
Various techniques for predicting instruction fetch widths. In one embodiment, a fetch prediction unit in a processor is configured to generate a fetch width...
US-9,367,470 Bounded cache searches
Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the...
US-9,367,469 Storage system and cache control method
A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple...
US-9,367,468 Data cache way prediction
In a particular embodiment, a method includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively...
US-9,367,467 System and method for managing cache replacements
A system and method for managing cache replacements and a memory subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a...
US-9,367,466 Conditional prefetching
A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a...
US-9,367,465 Method and system for improving memory access performance
The present invention relates to a computing system which includes a processor and a memory. It also includes a memory access optimizer which is arranged to...
US-9,367,464 Cache circuit having a tag array with smaller latency than a data array
A method is described that includes alternating cache requests sent to a tag array between data requests and dataless requests.
US-9,367,463 System and method utilizing a shared cache to provide zero copy memory mapped database
Methods and systems for providing a plurality of applications with concurrent access to data are disclosed. One such method includes identifying attributes of...
US-9,367,462 Shared memories for energy efficient multi-core processors
Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a...
US-9,367,461 Ordering constraint management within coherent memory systems
A data processing system including multiple processors 6, 8, 10, 12 each with a local cache memory 14, 16, 18, 20 share a main memory 24 under control of a...
US-9,367,460 Implicit I/O send on cache operations
A computer system for implicit input-output send on cache operations of a central processing unit is provided. The computer system comprises an aggregation...
US-9,367,459 Scheduling method and multi-core processor system
A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when...
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