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Patent # Description
US-9,367,358 Virtualizing a set of managers to form a composite manager in an autonomic system
A composite manager may include a set of managers virtualized as a single entity. The composite manager may also include at least one of a module to provide a...
US-9,367,357 Simultaneous scheduling of processes and offloading computation on many-core coprocessors
Methods and systems for scheduling jobs to manycore nodes in a cluster include selecting a job to run according to the job's wait time and the job's expected...
US-9,367,356 Resource access control
Various embodiments can control access to a computing resource (e.g., a memory resource) by detecting that a high priority activity is accessing the resource...
US-9,367,355 Resource utilization by one or more tasks
Complex devices, software systems, and/or networks may comprise one or more subsystems that perform periodic tasks. A first task may be assigned a first...
US-9,367,354 Queued workload service in a multi tenant environment
Tasks to be performed for a user can be outsourced to a workload service operable to process those types of tasks. Information for the tasks, such as code to be...
US-9,367,353 Storage control system with power throttling mechanism and method of operation thereof
A storage control system, and a method of operation thereof, including: a host interface module for receiving a host command from a host system; a power...
US-9,367,352 System and method for intelligent timer services
A method is provided for efficiently scheduling timer events within an operating system by allocating a plurality of timers, each of which has an expiry time,...
US-9,367,351 Profiling input/output behavioral characteristics in distributed infrastructure
Techniques for profiling input/output (I/O) characteristics in a computing system implemented with distributed infrastructure. In one example, a method...
US-9,367,350 Meta-scheduler with meta-contexts
A process in a computer system creates and uses a meta-scheduler with meta-contexts that execute on meta-virtual processors. The meta-scheduler includes a set...
US-9,367,349 Multi-core system and scheduling method
A multi-core system includes multiple processor cores; a bus connected to the processor cores; multiple peripheral devices accessed by the processor cores via...
US-9,367,348 Protecting the footprint of memory transactions from victimization
A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory...
US-9,367,347 Systems and methods for command execution order control in electronic systems
Systems and methods are provided for command execution. A stream-array data structure including a plurality of stream entries is received. One or more head...
US-9,367,346 Accelerating distributed transactions on key-value stores through dynamic lock localization
Systems and methods for accelerating distributed transactions on key-value stores includes applying one or more policies of dynamic lock-localization, the...
US-9,367,345 Power efficient cross-VCPU notification by VM function
A hypervisor configures a VM function component for execution on behalf of a guest operating system of a virtual machine, the VM function component to send a...
US-9,367,344 Optimized assignments and/or generation virtual machine for reducer tasks
The present disclosure relates to assignment or generation of reducer virtual machines after the "map" phase is substantially complete in MapReduce. Instead of...
US-9,367,343 Dynamic batch management of shared buffers for virtual machines
Methods, systems, and computer program products for providing dynamic batch management of shared packet buffers are disclosed. A virtualized computer system may...
US-9,367,342 Optimizing a deactivation process for a virtual machine system
A virtual machine system includes one or more virtual machines and a deactivator that deactivates the virtual machines. Each virtual machine includes an output...
US-9,367,341 Encrypting and decrypting virtual disk content using a single user sign-on
A mechanism for automatically encrypting and decrypting virtual disk content using a single user sign-on is disclosed. A method of embodiments of the invention...
US-9,367,340 Resource management method and apparatus for virtual machine system, and virtual machine system
An embodiment of the present invention provides a resource management method for a virtual machine system, where the method includes: obtaining, by a virtual...
US-9,367,339 Cryptographically attested resources for hosting virtual machines
Approaches to enable the configuration of computing resources for executing virtual machines on behalf of users to be cryptographically attested to or verified....
US-9,367,338 Dynamically binding data in an application
A computer-usable storage medium that when executed cause a computer system to perform a method for binding data in an application. An expression is created via...
US-9,367,337 Cloud-based personalization of shared resources
Methods and systems for personalization in a shared environment are provided. Information is stored in memory regarding the shared environment to which a...
US-9,367,336 Personalization of shared resources
Methods and systems for personalization in a shared environment are provided. Information is stored in memory regarding the shared environment to which a...
US-9,367,335 State dependent optimization for sequential booting of heterogeneous systems
A method and computer program product for implementing the method, where the method comprises obtaining boot dependencies among a plurality of systems, wherein...
US-9,367,334 Vibrator and audio resource sharing for mobile communication device
A communication device includes at least two output apparatuses, and an interface circuit configured as an interface between the at least two output apparatuses...
US-9,367,333 Booting a printer
A method for booting a printer includes storing a configuration image of the printer on a network storage device. The configuration image includes an...
US-9,367,332 Sensing data reading device and method
A sensing data reading device and method applied to an electronic device are provided. The sensing data reading device supports a first operating system and a...
US-9,367,331 Multi-environment operating system
A device with multiple, co-existing, and independent environments interacting with a common kernel, and related methods of operation, are disclosed herein....
US-9,367,330 Method of accessing files in electronic devices
In a method for accessing files in an electronic device, a Random Access Memory (RAM) disk is set-up to store the file system root of the electronic device. At...
US-9,367,329 Initialization of multi-core processing system
This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using...
US-9,367,328 Out-of-band host OS boot sequence verification
Embodiments of techniques and systems for out-of-band verification of host OS components are described. In embodiments, a out-of-band host OS boot sequence...
US-9,367,327 Method to ensure platform silicon configuration integrity
Some aspects include beginning a power on self test (POST) by a BIOS for a computer system; enumerating the computer system by the BIOS; providing, based on the...
US-9,367,326 Multiprocessor system and task allocation method
A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating...
US-9,367,325 Common architecture state presentation for processor having processing cores of different types
A method is described that includes deciding to migrate a thread from a first processing core to a second processing core. The method also includes...
US-9,367,324 Saving/restoring selected registers in transactional processing
A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be...
US-9,367,323 Processor assist facility
An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The...
US-9,367,322 Age based fast instruction issue
In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue...
US-9,367,321 Processor instruction set for controlling an event source to generate events used to schedule threads
The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the...
US-9,367,320 Techniques for hybrid computer thread creation and management
A technique for operating a computer system to support an application, a first application server environment, and a second application server environment...
US-9,367,319 System and method for a multi-schema branch predictor
A system and method for predicting the execution of a branch of computer-executable instructions. In an embodiment, a branch predictor may include a...
US-9,367,318 Doubling thread resources in a processor
Methods and systems are provided for managing thread execution in a processor. Multiple instructions are fetched from fetch queues. The instructions satisfy the...
US-9,367,317 Loop streaming detector for standard and complex instruction types
A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is...
US-9,367,316 Run-time instrumentation indirect sampling by instruction operation code
Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by instruction operation code. An aspect of the invention...
US-9,367,315 Image processing semiconductor device and image processing device
Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input...
US-9,367,314 Converting conditional short forward branches to computationally equivalent predicated instructions
A processor is operable to process conditional branches. The processor includes instruction fetch logic to fetch a conditional short forward branch. The...
US-9,367,313 Run-time instrumentation directed sampling
The invention relates to implementing run-time instrumentation directed sampling. An aspect of the invention includes a method for implementing run-time...
US-9,367,312 Processor efficiency by combining working and architectural register files
A processor includes an execution pipeline configured to execute instructions for threads, wherein the architectural state of a thread includes a set of...
US-9,367,311 Multi-core processor system, synchronization control system, synchronization control apparatus, information...
A multi-core processor system includes a given core that includes a detecting unit that detects migration of a thread under execution by a synchronization...
US-9,367,310 Stack access tracking using dedicated table
A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information...
US-9,367,309 Predicate attribute tracker
In an embodiment, a processor includes a register attribute tracker configured to track one or more attributes corresponding to registers. The register...
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