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Semiconductor device and method of manufacturing the same
An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric...
Memory structure device having a buried gate structure
A semiconductor device including a storage node contact that surrounds three sidewalls of an active region to increase the contact area between the storage node...
FinFET devices including epitaxially grown device isolation regions, and a
method of manufacturing same
A method for manufacturing a semiconductor device including a plurality of fin field-effect transistor (FinFET) devices, comprises forming a plurality of fins...
Multi-layer semiconductor structures for fabricating inverter chains
Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first...
CMOS device with improved accuracy of threshold voltage adjustment and
method for manufacturing the same
An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate...
Analog circuit cell array having some transistors that include two
connected gate electrodes and two connected...
An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first...
Series connected transistor structure and method of manufacturing the same
A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a...
High voltage resistor with high voltage junction termination
Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The...
Integrated FinFET capacitor
A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a...
High current, low switching loss SiC power module
A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules...
Electrostatic protective device
The present invention discloses an electrostatic protective device structure, which comprises a CMOS transistor that is disposed entirely above a P-type silicon...
Bipolar transistor including lateral suppression diode
A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a...
Transistor assembly as an ESD protection measure
A diode (23) is arranged near a transistor (25) to protect from ESD. The diode comprises a well (5) of a first conductivity type and a doped region (4) of a...
Amplifier voltage limiting using punch-through effect
Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (TSV) positioning. A semiconductor die is...
Electrostatic discharge protection circuits and methods
An electrostatic discharge (ESD) protection circuit includes an electrostatic discharge bus, first and second resistors coupled in series, first and second...
Semiconductor integrated circuit device
First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second...
Process for forming package-on-package structures
A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the...
Bump package and methods of formation thereof
In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a...
Light emitting device for linear light source
A light emitting device includes a substrate; a first metal film formed on the substrate; a plurality of light emitting elements arranged in a line, each...
Light emitting diode package
Provided is a light emitting diode package including: a molded portion having a housing; a plurality of light emitting chips housed in the housing; a plurality...
Light-emitting device array with individual cells
A light-emitting device and a method for manufacturing the light-emitting device is disclosed. Such a light-emitting device comprises a substrate, a plurality...
DIE packages and methods of manufacture thereof
Die packages and method of manufacturing the same are disclosed. In an embodiment, a method of manufacturing a die package may include forming an encapsulated...
Interconnect structures for wafer level package and methods of forming
A device package includes a plurality of dies, a molding compound extending along sidewalls of the plurality of dies, and a polymer layer over and contacting...
Reflow process and tool
Reflow processes and apparatuses are disclosed. A process includes enclosing a package workpiece in an enclosed environment of a chamber of a reflow tool;...
Wire structure and semiconductor device having the same, and method of
manufacturing the wire structure
According to example embodiments, a wire structure includes a first wire that includes a first wire core and a first carbon shell surrounding the first wire...
Semiconductor substrate, semiconductor package structure and method of
making the same
The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a...
Package substrate structure for enhanced signal transmission and method
In one embodiment, an electronic package structure includes a substrate having one or more conductive plane layers formed therein. The substrate also includes a...
Methods and apparatus for package on package devices
Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom...
Connector structures of integrated circuits
A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the...
Chip package and method thereof
The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at...
Passivated copper chip pads
A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active...
Mounting structure and manufacturing method for same
In a provided mounting structure, an electronic component such as a semiconductor chip having a fragile film is mounted on a substrate such as a circuit board...
Under bump metallization
A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed...
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface,...
Arrangement for energy conditioning
Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition...
Semiconductor device for preventing crack in pad region and fabricating
A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is...
Integrated circuit bonding with interposer die
A method of bonding components is disclosed. One embodiment of such a method includes applying both heat and pressure to a stack of components that includes an...
Display substrate and manufacturing method thereof as well as display
The embodiments of the present invention provide a display substrate and a manufacturing method thereof, as well as a display device including the display...
Stacked microelectronic dice embedded in a microelectronic substrate
Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one...
Stacked electronic device
An electronic component device, includes, a plurality of wiring layers including a component connection pad in a center part and an external connection pad in a...
Copper etching integration scheme
The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a...
Polymer member based interconnect
An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130), possibly dielectric, coated with...
Methods and apparatuses to form self-aligned caps
At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The...
High quality factor filter implemented in wafer level packaging (WLP)
Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor...
Self aligned via in integrated circuit
A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic...
Interconnect structure and method for forming the same
Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric...
Dual hard mask lithography process
A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second...
Protecting layer in a semiconductor structure
A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The...
Semiconductor device and method of forming interconnect structure with
conductive pads having expanded...
A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is...
Hybrid semiconductor package
A semiconductor package includes a substrate, an RF semiconductor die attached to a first side of the substrate, a capacitor attached to the first side of the...