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Patent # Description
US-9,373,576 Flip chip pad geometry for an IC package substrate
An integrated circuit (IC) package substrate is provided. In one embodiment, the IC package substrate includes a dielectric layer having first and second...
US-9,373,575 TSV structures and methods for forming the same
A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive...
US-9,373,574 Semiconductor packages and methods of forming the same
Disclosed are semiconductor packages and methods of forming the same. In the semiconductor packages and the methods, a package substrate includes a hole not...
US-9,373,573 Solder joint flip chip interconnection
A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate...
US-9,373,572 Semiconductor package having etched foil capacitor integrated into leadframe
A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and...
US-9,373,571 Integrating multi-output power converters having vertically stacked semiconductor chips
An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first...
US-9,373,570 Semiconductor module and driving device for switching element
A semiconductor module includes: a semiconductor element; first and second main current passages for energizing the semiconductor element, the first and second...
US-9,373,569 Flat no-lead packages with electroplated edges
A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad,...
US-9,373,567 Lead frame, manufacture method and package structure thereof
Disclosed herein are various chip lead frame and packaging structures, and methods of fabrication. In one embodiment, a lead frame can include: (i) a horizontal...
US-9,373,566 High power electronic component with multiple leadframes
In an embodiment an electronic component includes a semiconductor die having a first surface, the first surface including a first current electrode and a...
US-9,373,565 Stub minimization for assemblies without wirebonds to package substrate
A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are...
US-9,373,564 Semiconductor device, manufacturing method and stacking structure thereof
A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a...
US-9,373,563 Semiconductor assembly having a housing
A semiconductor assembly, power semiconductor module, a housing and methods for assembling the power semiconductor housing is disclosed. One embodiment provides...
US-9,373,562 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device provided herewith includes a semiconductor substrate; a brazing material bonded to the semiconductor substrate; a heat sink connected to...
US-9,373,561 Integrated circuit barrierless microfluidic channel
A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This...
US-9,373,560 Drive circuit device
A drive circuit device includes a circuit board having a multilayer structure, which includes first to fourth circuit conductor layers, and first to third...
US-9,373,559 Low-stress dual underfill packaging
The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses,...
US-9,373,558 Resin-sealed electronic control device
The present invention is intended to increase the moisture resistance of a resin-sealed electronic control device. The resin-sealed electronic control device...
US-9,373,557 Enhanced modularity in heterogeneous 3D stacks
A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a...
US-9,373,556 Module IC package structure and method for manufacturing the same
A module IC package structure for increasing heat-dissipating efficiency includes a substrate unit, an electronic unit, a package unit, a first heat-dissipating...
US-9,373,555 Power semiconductor module, method for manufacturing the same, and power converter
A power semiconductor module includes a metal plate having a through hole with an eaves; an insulated metal block including a metal block having an element...
US-9,373,554 Organic light emitting diode fabrication with hole transport/injection layer thickness measurement
A method of monitoring an OLED production process for making an OLED device is disclosed. According to the method, at least one reference OLED device similar to...
US-9,373,553 Resin application apparatus, optical property correction apparatus and method, and method for manufacturing LED...
A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED)...
US-9,373,552 Method of calibrating or exposing a lithography tool
A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes...
US-9,373,551 Moveable and adjustable gas injectors for an etching chamber
An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality...
US-9,373,550 Selectively degrading current resistance of field effect transistor devices
A method includes selectively degrading a current capacity of a first finned-field-effect-transistor (finFET) relative to a second finFET by forming a material...
US-9,373,549 Semiconductor device and method of forming the same
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate...
US-9,373,548 CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of...
A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress...
US-9,373,547 Large-scale patterning of germanium quantum dots by stress transfer
Provided is a method for forming a two-dimensional array of semiconductor quantum confined structures. The method includes providing a layer that has first...
US-9,373,546 Self aligned replacement Fin formation
Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET...
US-9,373,545 Semiconductor structure including a through electrode, and method for forming the same
A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned...
US-9,373,544 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially...
US-9,373,543 Forming interconnect features with reduced sidewall tapering
A method includes forming a stack of materials including a first dielectric layer having a conductive feature positioned therein, and a second dielectric layer...
US-9,373,542 Integrated circuits and methods for fabricating integrated circuits with improved contact structures
Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an...
US-9,373,541 Hard mask removal scheme
A method includes forming a barrier layer in a via hole and over a hard mask layer. The hard mask layer is disposed over a dielectric layer. The via hole is...
US-9,373,540 Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating...
US-9,373,539 Collapsible probe tower device and method of forming thereof
A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a...
US-9,373,538 Interconnect level structures for confining stitch-induced via structures
A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A...
US-9,373,536 Stress reduction apparatus
A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower...
US-9,373,535 T-shaped fin isolation region and methods of fabrication
Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit...
US-9,373,534 Rotary positioning apparatus with dome carrier, automatic pick-and-place system, and operating method thereof
A rotary positioning apparatus includes a fixing base, a rotation mechanism, two driving modules and a carrier. The rotation mechanism is disposed on the fixing...
US-9,373,533 Systems and methods for providing wafer access in a wafer processing system
Systems and methods for providing wafer access in a wafer processing system are disclosed herein. The methods may include docking a first wafer cassette on the...
US-9,373,532 Guide apparatus, exposure apparatus, and method of manufacturing article
The present invention provides a guide apparatus including a guide member located on a base, and a moving member movable along the guide member. The guide...
US-9,373,531 Substrate transfer device, substrate processing apparatus, and substrate accommodation method
A substrate can be appropriately accommodated in a cassette. A substrate transfer device includes a substrate transfer unit that delivers the substrate with...
US-9,373,530 Tool for picking a planar object from a supply station
A pick tool for picking a planar object from a supply station is presented, in particular to be used for picking a semiconductor die from a carrier tape, said...
US-9,373,529 Process tool having third heating source and method of using the same
A processing tool includes a chamber configured to receive a wafer, the chamber having a sidewall and a sidewall heating source configured to heat the sidewall...
US-9,373,528 Substrate processing apparatus
A substrate processing apparatus 1 includes a substrate processing unit 40 configured to process a substrate W by supplying a mixed liquid M of a first liquid C...
US-9,373,527 Chip on package structure and method
A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the...
US-9,373,526 Chip package and method for forming the same
According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein...
US-9,373,525 Method for manufacturing semiconductor device
An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed...
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