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Method of accessing a core of a nuclear reactor
A telescoping guide for extraction and reinsertion support handling of in-core instrument thimble assemblies in the area above the upper support plate in the...
A memory device including a first cell block including a plurality of word lines and first to K.sup.th (K is a natural number) redundancy word lines, a second...
Semiconductor apparatus with repair information control function
A semiconductor apparatus may include a global line configured to enable electrical coupling between a memory block and an input/output terminal, a fuse array...
Semiconductor test device
A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating...
Semiconductor memory apparatus and operating method thereof
A semiconductor memory apparatus includes: a user setting unit configured to generate test data and a delay control signal in response to an external command...
Circuit and data processor with headroom monitoring and method therefor
A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a...
Circuit and method for testing memory devices
The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address...
Method and system for testing a memory
A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be...
Dynamic hard error detection
A method of testing a circuit includes halting a flow of normal data through the circuit, running test data through the circuit while subjecting the circuit to...
Shift register unit and gate drive device for liquid crystal display
A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to...
Shift register unit, shift register circuit, array substrate and display
A shift register unit, a shift register circuit, an array substrate and a display device can avoid a phenomenon that light lines and dark lines appear...
System and method of programming a memory cell
An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a...
Antifuse control circuit and antifuse reading method
A method of reading an antifuse in a semiconductor memory device during a power-up routine includes; generating a read voltage used during an antifuse read...
MLC OTP operation in A-Si RRAM
Providing for a memory cell capable of operating a one time programmable, multi-level cell memory is described herein. In some embodiments, a program signal...
Systems and methods for reduced program disturb for 3D NAND flash
Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb....
Highly linear analog-to-digital converter and method for nonvolatile
A non-volatile memory has an ADC that digitizes an analog voltage in a range delimited by V1 and V2 into N intervals, resulting in a digital Vx with x between 1...
Non-volatile memory device with current injection sensing amplifier
A non-volatile memory device with a current injection sensing amplifier is disclosed.
Flash memory based on storage devices and methods of operation
A method transfers read data from a flash memory to a controller synchronously with respect to a data strobe signal during a read data transfer period. During...
Auto resume of irregular erase stoppage of a memory sector
Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory...
Sensing memory cells coupled to different access lines in different blocks
of memory cells
In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the...
3D NAND memory device and operation thereof
The present invention relates to 3D memory devices and methods for programming such devices, and more particularly to memory devices having control circuitry...
Semiconductor memory device including a dummy memory cell and method of
programming the same
A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of...
Method of programming non-volatile memory device and apparatuses for
performing the method
A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an...
Vertical structure semiconductor memory devices and methods of
manufacturing the same
A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed...
Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
Prototyping integrated circuit devices with programmable impedance
A method can include programming programmable resistive elements (PREs) in a first integrated circuit (IC) device to establish functions of configurable...
Page programming sequences and assignment schemes for a memory device
Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the...
Side wall bit line structures
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage...
Apparatus to reduce retention failure in complementary resistive memory
Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory...
Reference column of semiconductor memory, and electronic device including
A reference column of a semiconductor memory includes a reference bit line; a reference source line; and first to N.sup.th resistive memory cells disposed...
Resistive memory device implementing selective memory cell refresh
A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the...
Memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,...
Resistive memory apparatus
A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes...
Semiconductor memory device and method of programming the same
A semiconductor memory device, may include a memory cell array including memory cells, in which a page to be programmed within the memory cell array may...
Semiconductor memory device
A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern includes...
Sense amplifier with pulsed control for pull-up transistors
A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed...
Static random access memory (SRAM) arrays having substantially constant
operational yields across multiple...
Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one...
Dual-port SRAM systems
Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell...
Semiconductor memory and method for operating the same
A semiconductor memory may include: a bank control signal generation unit suitable for sequentially generating a plurality of bank control signals for...
Integrated circuit device having programmable input capacitance
An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may...
STT-MRAM sensing technique
Embodiments are directed to a system for sensing a data state of a selected memory cell. The system includes a first reference cell, a sample-and-hold sense...
Method for healing phase-change memory device and applications thereof
A method for healing phase-change memory device includes steps as follows: At least one memory cell comprising a phase-change material with a shifted...
System including memories sharing calibration reference resistor and
calibration method thereof
A semiconductor apparatus includes a first memory, a second memory, and a shared reference resistor. The first memory is electrically coupled to the shared...
Multi-port semiconductor memory device with multi-interface
A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a...
Active control device and semiconductor device including the same
An active control device and a semiconductor device including the same are disclosed, which can control an active command in response to a pin change of a...
Semiconductor device for driving sub word lines
The semiconductor device incorporates a selected sub word line driver and a first voltage switching circuit. The selected sub word line driver has an input node...
Apparatuses, integrated circuits, and methods for testmode security
Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store...
Latency control circuit and semiconductor apparatus using the same
A latency control circuit may include a first latency control section configured to control a latency of a delay-locked termination signal according to a first...
Non-volatile memory validity
An embodiment provides a method, including: reading validity timing information written to a non-volatile memory device; and determining validity of the...
Semiconductor apparatus capable of self-tuning a timing margin
A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal...