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Patent # Description
US-9,372,818 Proactive quality of service in multi-matrix system bus
A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a...
US-9,372,817 High perfomance DMA controller for video processors
This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and...
US-9,372,816 Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit
Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique...
US-9,372,815 Estimating processor load using peripheral adapter queue behavior
Techniques for estimating processor load by using queue depth information of a peripheral adapter provides processor loading information that can be used to...
US-9,372,814 System and method for transferring an active state between a powerful processor and a less powerful processor
An information handling system includes a tablet with a processor, and a dock with a second processor that determines that the tablet is coupled to the dock,...
US-9,372,813 Remote-key based memory buffer access control mechanism
A system and method implementing revocable secure remote keys is disclosed. A plurality of indexed base secrets is stored in a register of a coprocessor of a...
US-9,372,812 Determining policy actions for the handling of data read/write extended page table violations
Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are...
US-9,372,811 Retention priority based cache replacement policy
A data processing system includes a cache memory 58 and cache control circuitry 56 for applying a cache replacement policy based upon a retention priority value...
US-9,372,810 Collaborative caching
A method is provided for collaborative caching between a server cache (104) of a server computer (102) and an array cache (112) of a storage array (110) coupled...
US-9,372,809 System and method for storing data off site
A system and method for efficiently storing data both on-site and off-site in a cloud storage system. Data read and write requests are received by a cloud data...
US-9,372,808 Deadlock-avoiding coherent system on chip interconnect
This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked...
US-9,372,807 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-9,372,806 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-9,372,805 Operating on translation look-aside buffers in a multiprocessor environment
An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions...
US-9,372,804 Cache memory for hybrid disk drives
A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of...
US-9,372,803 Method and system for shutting down active core based caches
A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache...
US-9,372,802 Data writing method, hard disc module, and data writing system
A data writing method, a hard disc module, and a data writing system for writing data into the hard disc module are provided, wherein the hard disc module...
US-9,372,801 Managing a cache in a multi-node virtual tape controller
A method according to one embodiment includes outputting a first alert when a cache free space size is less than a first threshold and entering into a warning...
US-9,372,800 Inter-chip interconnect protocol for a multi-chip system
A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a...
US-9,372,799 Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a...
US-9,372,798 Data processing apparatus having first and second protocol domains, and method for the data processing apparatus
A data processing apparatus (2) comprises a first protocol domain A configured to operate under a write progress protocol and a second protocol domain B...
US-9,372,797 Adaptively enabling and disabling snooping fastpath commands
Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling...
US-9,372,796 Optimum cache access scheme for multi endpoint atomic access in a multicore system
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
US-9,372,795 Apparatus and method for maintaining cache coherency, and multiprocessor apparatus using the method
Provided are an apparatus and method for maintaining cache coherency, and a multiprocessor apparatus using the method. The multiprocessor apparatus includes a...
US-9,372,794 Using logical block addresses with generation numbers as data fingerprints to provide cache coherency
The technique introduced here involves using a block address and a corresponding generation number as a "fingerprint" to uniquely identify a sequence of data...
US-9,372,793 System and method for predictive caching
A method, computer program product, and computing system for monitoring an application being executed on a host to generate a prediction concerning a quantity...
US-9,372,792 Advanced management of a non-volatile memory
A method of managing a non-volatile memory module, the method may include: receiving data sectors during a set of at least one write transactions; selecting,...
US-9,372,791 Method for masking the end-of-life transition of an electronic device and device comprising a corresponding...
The invention relates to a method for masking the end-of-life transition of an electronic microprocessor device comprising a reprogrammable non-volatile memory...
US-9,372,790 Nonvolatile memory device having wear-leveling control and method of operating the same
A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes...
US-9,372,789 Log-structured filed system with file branching
Disclosed are systems, computer-readable mediums, and methods for reading a sequence number from regions of a solid state storage device. A latest region is...
US-9,372,788 Storage system and method of adjusting spare memory space in storage system
A method includes determining a size of a recommended spare memory space of each of one or more storage nodes based on a state of the storage nodes, and...
US-9,372,787 System and method for automating testing
According to some embodiments, a method and apparatus are provided to receive browser automation code to automatically test a software application executed in a...
US-9,372,786 Constructing state-transition functions for mobile devices
Disclosed are various embodiments for a state monitoring application. A state monitoring application initiates the execution of test operations on a client...
US-9,372,785 Identifying implicit assumptions associated with a software product
A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit...
US-9,372,784 Test system configuration method and system
This disclosure relates to computer test systems and, more particularly, to automatically configuring computer test systems. A method, computer program product,...
US-9,372,783 Recording the core data of a computer process which provides trace data
A method, apparatus and computer program for recording the core data of a computer process, the computer process comprising trace points and core data is...
US-9,372,782 Dynamic tracing framework for debugging in virtualized environments
Embodiments of the present invention provide a system and method for a dynamic tracing framework for debugging in a virtualized environment. Embodiment of the...
US-9,372,781 Program subset execution and debug
In response to identification of an error in operation of a system, a debugging module determines where to set a debug entry point for a program subset debug...
US-9,372,780 Breakpoint continuation for stream computing
A first stream operator in a stream computing application receives and processes a first stream of tuples. The processing at the first stream operator is paused...
US-9,372,779 System, method, apparatus and computer program for automatic evaluation of user interfaces in software programs
A method includes inputting an application program to be tested to a data processing system; linking the application program to a software library; performing,...
US-9,372,778 Collaborative based caching
A computer-implemented method for collaborative caching of files during a collaboration session includes receiving a request from a first electronic device for...
US-9,372,777 Collecting and attaching a bug trace to a problem information technology ticket
Methods and arrangements for enhancing a ticket relative to user interaction with a system. An information technology ticket related to user interaction with an...
US-9,372,776 Monitoring user activity and performance of computerized devices
The presently disclosed subject matter includes a device, system and method for monitoring activity at a computerized device, the device running one or more...
US-9,372,775 Method and apparatus for providing at risk information in a cloud computing system having redundancy
Methods and apparatus for generating at risk probabilities for a pre-integrated cloud computing system. In one embodiment, a system determines a revised overall...
US-9,372,774 Redundant computing architecture
A redundant computing architecture includes a first control unit, a second control unit, and a switch. The first control unit is configured to provide a first...
US-9,372,773 User-level hardware branch records
A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and...
US-9,372,772 Co-verification--of hardware and software, a unified approach in verification
A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are...
US-9,372,771 Method of grouping embedded memories for testing
A method of ganging memories in an Integrated Circuit (IC) design identifies a first subset of a first set of the memories that have word counts in a common...
US-9,372,770 Hardware platform validation
A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a...
US-9,372,769 Server and inspecting method thereof
Disclosed herein are a server and an inspecting method thereof. The server comprises a baseboard management controller (BMC), a non-volatile memory coupled with...
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