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Patent # Description
US-9,379,230 Semiconductor crystal substrate, manufacturing method of semiconductor crystal substrate, manufacturing method...
A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is...
US-9,379,229 Semiconductor apparatus including protective film on gate electrode and method for manufacturing the...
A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed...
US-9,379,228 Heterojunction field effect transistor (HFET) variable gain amplifier having variable transconductance
A heterojunction semiconductor field effect transistor HFET having a pair of layers of different semiconductor materials forming a quantum well within the...
US-9,379,227 High-electron-mobility transistor
A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas...
US-9,379,226 Semiconductor wafer and insulated gate field effect transistor
Provided is a technique capable of realizing an insulated gate (MIS-type) P-HEMT structure with good transistor characteristics such as an improved carrier...
US-9,379,225 Semiconductor device
A semiconductor device in which an IGBT region and a diode region are formed on one semiconductor substrate is disclosed. The IGBT region includes: a body layer...
US-9,379,224 Semiconductor device
A semiconductor device in which a diode region and an IGBT region are formed on a same semiconductor substrate is provided. The diode region includes a...
US-9,379,223 Oxide semiconductor film, semiconductor device, and manufacturing method of semiconductor device
A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used....
US-9,379,222 Method of making a split gate non-volatile memory (NVM) cell
Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy...
US-9,379,221 Bottom-up metal gate formation on replacement metal gate finFET devices
A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and method of fabricating a finFET device with...
US-9,379,220 FinFET device structure and methods of making same
Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of...
US-9,379,219 SiGe finFET with improved junction doping control
A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a...
US-9,379,218 Fin formation in fin field effect transistors
A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon...
US-9,379,217 FinFETs and the methods for forming the same
A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A...
US-9,379,216 Semiconductor device and method for manufacturing same
According to an embodiment, a method for manufacturing a semiconductor device includes forming a gate trench extending into a first semiconductor layer; forming...
US-9,379,215 Fin field effect transistor
A method of fabricating a fin field effect transistor (FinFET) including forming a first insulation region and a second insulation region and fin there between....
US-9,379,214 Reduced variation MOSFET using a drain-extension-last process
A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain...
US-9,379,213 Method for forming doped areas under transistor spacers
Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel...
US-9,379,212 Extended-drain transistor using inner spacer
An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner...
US-9,379,211 Fabricating method of semiconductor device
A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over...
US-9,379,210 Sacrificial pre-metal dielectric for self-aligned contact scheme
Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process...
US-9,379,209 Selectively forming a protective conductive cap on a metal gate electrode
A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric...
US-9,379,208 Integrated circuits and methods of forming integrated circuits
A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate...
US-9,379,207 Stable nickel silicide formation with fluorine incorporation and related IC structure
A method of forming a stable nickel silicide layer is provided. The method may include forming a nickel silicide layer on a substrate. A fluorine-rich nickel...
US-9,379,206 Semiconductor device and fabrication method thereof
A semiconductor device fabrication method is provided in which recesses are formed at source/drain positions in the substrate, removable sidewalls are formed on...
US-9,379,205 Semiconductor device
A semiconductor device includes: a semiconductor multi-layer structure which includes at least an electron traveling layer and an electron supply layer on a...
US-9,379,204 Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched...
US-9,379,203 Ultra-fast breakover diode
An ultra-fast breakover diode has a turn on time T.sub.ON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and...
US-9,379,202 Decoupling capacitors for interposers
Embodiments of the invention generally relate to interposers for packaging integrated circuits. The interposers include capacitive devices for reducing signal...
US-9,379,201 Electrostatic discharge diodes and methods of forming electrostatic discharge diodes
A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a...
US-9,379,200 Memory with a silicide charge trapping layer
A semiconductor device according to the present embodiment includes a semiconductor substrate. A first insulating film is provided on the semiconductor...
US-9,379,199 Semiconductor device including a contact plug with barrier materials
Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a...
US-9,379,198 Integrated circuit structure having selectively formed metal cap
An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit...
US-9,379,197 Recess array device
A recess array device includes a semiconductor substrate and at least an active area in a main surface of the semiconductor substrate. A gate trench penetrates...
US-9,379,196 Method of forming a trench using epitaxial lateral overgrowth and deep vertical trench structure
In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first...
US-9,379,195 HEMT GaN device with a non-uniform lateral two dimensional electron gas profile and method of manufacturing the...
A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a...
US-9,379,194 Floating gate NVM with low-moisture-content oxide cap layer
A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress...
US-9,379,193 Semiconductor package for a lateral device and related methods
A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and...
US-9,379,192 Semiconductor device
A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a source electrode layer and a drain electrode...
US-9,379,191 High electron mobility transistor including an isolation region
A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer...
US-9,379,190 Crystalline multilayer structure and semiconductor device
Provided is a crystalline multilayer structure which has good electrical properties and is useful for semiconductor devices. A crystalline multilayer structure...
US-9,379,189 Method and system for transient voltage suppression
A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a...
US-9,379,188 Insulated gate bipolar transistor structure having low substrate leakage
A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor...
US-9,379,187 Vertically-conducting trench MOSFET
A semiconductor device and a fabricating method thereof are provided. The semiconductor device include: a trench disposed within a substrate, the trench...
US-9,379,186 Fet structure for minimum size length/width devices for performance boost and mismatch reduction
Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate...
US-9,379,185 Method of forming channel region dopant control in fin field effect transistor
A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions...
US-9,379,184 Secure chip with physically unclonable function
A first trench having a first aspect ratio and a second trench having a second aspect ratio that is greater than the first trench are provided into a material...
US-9,379,183 Methods for manufacturing integrated circuit devices having features with reduced edge curvature
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution...
US-9,379,182 Method for forming nanowire and semiconductor device formed with the nanowire
A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top...
US-9,379,181 Semiconductor device
A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided....
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