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Patent # Description
US-9,379,129 Assist gate structures for three-dimensional (3D) vertical gate array memory structure
A 3D array of memory cells with one or more blocks is described. The blocks include a plurality of layers. The layers in the plurality include semiconductor...
US-9,379,128 Split gate non-volatile memory device and method for fabricating the same
A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO...
US-9,379,127 Semiconductor device and manufacturing method of semiconductor device
A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a...
US-9,379,126 Damascene conductor for a 3D device
A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active...
US-9,379,125 Semiconductor device with a pillar-shaped semiconductor layer
A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that...
US-9,379,124 Vertical floating gate NAND with selectively deposited ALD metal films
A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes...
US-9,379,123 Semiconductor memory devices and methods of fabricating the same
Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a...
US-9,379,122 Memory device and method of fabricating the same
A memory device includes an array of floating gate memory cells. Adjacent memory cells are separated by a plurality of air gaps that electrically decouple...
US-9,379,121 Split gate non-volatile flash memory cell having metal gates and method of making same
A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second...
US-9,379,120 Metal control gate structures and air gap isolation in non-volatile memory
High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures...
US-9,379,119 Static random access memory
A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes:...
US-9,379,118 Methods of fabricating semiconductor devices including interlayer wiring structures
Semiconductor devices and methods of fabricating the same are disclosed. The methods include forming a first interlayer insulating layer and a conductive...
US-9,379,117 Semiconductor device with buried bit line and method for fabricating the same
A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in...
US-9,379,116 Fabrication of a deep trench memory cell
A method including forming a buffer layer between a top pad layer and a bottom pad layer all above a deep trench capacitor embedded in a substrate, forming a...
US-9,379,115 Semiconductor device having a resistor and methods of forming the same
In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least...
US-9,379,114 Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other...
US-9,379,113 Programmable logic device and method for manufacturing semiconductor device
To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation...
US-9,379,112 Integrated circuit with transistor array and layout method thereof
An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together....
US-9,379,111 Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin...
A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches...
US-9,379,110 Method of fabrication of ETSOI CMOS device by sidewall image transfer (SIT)
Disclosed is a process to prepare extremely thin semiconductor on insulator complementary metal-oxide-semiconductor devices having n-type and p-type metal oxide...
US-9,379,109 Integrated circuit having improved radiation immunity
An integrated circuit device having improved radiation immunity is described. The integrated circuit device comprises an n-type wafer having a first surface and...
US-9,379,108 Contact structure of semiconductor device
A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second...
US-9,379,107 FinFET semiconductor devices including dummy structures
Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active...
US-9,379,106 Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels
A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the...
US-9,379,104 Method to make gate-to-body contact to release plasma induced charging
Methods for preparing a FinFET device with a protection diode formed prior to M1 formation and resulting devices are disclosed. Embodiments include forming...
US-9,379,103 Semiconductor device and method of preventing latch-up in a charge pump circuit
A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions...
US-9,379,102 Nitride-based semiconductor device
A nitride-based semiconductor diode includes a substrate, a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on...
US-9,379,101 Semiconductor integrated circuit device
In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the...
US-9,379,100 Semiconductor integrated circuit device
A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O...
US-9,379,099 ESD protection circuit and integrated circuit
An ESD protection circuit is cooperated with a high-frequency circuit and includes a silicon-controlled rectifier element and an inductive element. The...
US-9,379,098 Electrostatic discharge protection circuit including a distributed diode string
An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the...
US-9,379,097 Fan-out PoP stacking process
Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In...
US-9,379,096 Semiconductor device
A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor...
US-9,379,095 Photocoupler
A photocoupler includes: a support substrate; a MOSFET; a light receiving element; a light emitting element; and a bonding layer. The support substrate includes...
US-9,379,094 Light emitting device and method for manufacturing the same including a light-reflective resin
A light emitting device includes a substrate, a light-emitting diode chip mounted on the substrate, a Zener diode chip mounted next to the light-emitting diode...
US-9,379,093 Method and apparatus for image sensor packaging
Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are...
US-9,379,092 Micro device with stabilization post
A method and structure for stabilizing an array of micro devices is disclosed. A stabilization layer includes an array of stabilization cavities and array of...
US-9,379,091 Semiconductor die assemblies and semiconductor devices including same
Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice...
US-9,379,090 System, apparatus, and method for split die interconnection
A semiconductor package for a side by side die configuration may include a substrate having a cavity, a bridge interposer positioned within the cavity and...
US-9,379,089 Electrical system and core module thereof
Disclosed is a core module, comprising: a package substrate, having a plurality of pads; a first component, connected to the pads of the package substrate...
US-9,379,088 Stacked package of voltage regulator and method for fabricating the same
The present disclosure relates to a stacked package of a voltage regulator and a method for fabricating the same. The method comprises: providing a first chip...
US-9,379,087 Method of making a QFN package
A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and...
US-9,379,086 Method of manufacturing semiconductor device
A semiconductor device includes a common wire that sequentially connects three or more pads; bonding portions at which a side surface of the wire is bonded to...
US-9,379,085 Wire bonding structure of semiconductor device and wire bonding method
A wire bonding structure is provided which includes a wire having a first bonding portion and a second bonding portion. The first bonding portion is bonded to...
US-9,379,084 Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is...
US-9,379,083 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device is a composite module in which three power semiconductor modules are arranged at a predetermined interval in the same plane and...
US-9,379,082 Pressure application apparatus and pressure application method
A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy...
US-9,379,081 Semiconductor device package and method of the same
The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes...
US-9,379,080 Method and apparatus for a conductive pillar structure
A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed...
US-9,379,079 Flip chip scheme and method of forming flip chip scheme
The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of...
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