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Patent # Description
US-9,379,078 3D die stacking structure with fine pitches
A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package...
US-9,379,077 Metal contact for semiconductor device
A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the...
US-9,379,076 Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the...
US-9,379,075 Semiconductor device with bump stop structure
A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization...
US-9,379,074 Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of...
US-9,379,073 Multi-layer pad ring for integrated circuit
Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to...
US-9,379,072 Chip package and method for forming the same
A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second...
US-9,379,071 Single inline no-lead semiconductor package
Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure...
US-9,379,069 Semiconductor arrangement comprising transmission line surrounded by magnetic layer
A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer surrounding a first transmission line and a magnetic...
US-9,379,068 ESD protection semiconductor device
A semiconductor substrate (1) is provided with a source region (2) and a drain region (3) of a first type of electrical conductivity arranged at a surface (10)...
US-9,379,067 Semiconductor devices and methods of manufacture thereof having guard ring structure
In some embodiments, an integrated circuit (IC) device includes a substrate having a first functional region, a second functional region and a third functional...
US-9,379,066 Device for detecting a laser attack in an integrated circuit chip
A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate,...
US-9,379,065 Crack stopping structure in wafer level packaging (WLP)
Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a...
US-9,379,064 Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming...
A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented...
US-9,379,063 Semiconductor device and semiconductor chip
The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips...
US-9,379,062 Semiconductor package
Provided is a semiconductor package including a plurality of first semiconductor chips that are stacked on a substrate and a second semiconductor chip disposed...
US-9,379,061 High density dielectric etch-stop layer
Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an...
US-9,379,060 Graphene wiring
A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the...
US-9,379,059 Power and ground routing of integrated circuit devices with improved IR drop and chip performance
An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first...
US-9,379,058 Grounding dummy gate in scaled layout design
A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically...
US-9,379,057 Method and structure to reduce the electric field in semiconductor wiring interconnects
Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy...
US-9,379,056 Semiconductor structure and method for manufacturing the same
The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming...
US-9,379,055 Semiconductor device and method of manufacturing the same
A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first...
US-9,379,054 Chip on film and display apparatus
The present disclosure of the present invention provides a chip on film and a display apparatus. The chip on film comprises a substrate having an input end lead...
US-9,379,053 Semiconductor device having signal line and power supply line intersecting with each other
Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first...
US-9,379,052 Multi chip modules for downhole equipment
An electronic assembly for use in a downhole module may include a multilayer ceramic assembly and an electronic component disposed on the multilayer ceramic...
US-9,379,051 Semiconductor device
According to the present invention, a semiconductor having excellent yield is provided. The semiconductor device (10) of the present invention includes: a base...
US-9,379,050 Electronic device
An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical...
US-9,379,049 Semiconductor apparatus
The semiconductor apparatus includes: the first lead frame; the second lead frame; the second insulation resin which is disposed between the first lead frame...
US-9,379,048 Dual-flag stacked die package
In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and...
US-9,379,047 Semiconductor device
A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on...
US-9,379,046 Module comprising a semiconductor chip
A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a...
US-9,379,045 Common drain power clip for battery pack protection mosfet
A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40...
US-9,379,044 Package carrier, package carrier manufacturing method, package structure for semiconductor device and...
A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a...
US-9,379,043 TSV structure having insulating layers with embedded voids
Disclosed is a TSV structure having insulating layers with embedded voids, including a chip layer, a dielectric liner and a conductive filler. There is at least...
US-9,379,042 Integrated circuit devices having through silicon via structures and methods of manufacturing the same
An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a...
US-9,379,041 Fan out package structure
Packages and methods of forming packages are disclosed. In an example, a structure comprises a die comprising an electrical pad on an active side, and an...
US-9,379,040 Semiconductor device and method of manufacturing semiconductor device
According to one embodiment, a semiconductor device includes a first conductor, a second conductor, and an envelope. The first conductor includes a first...
US-9,379,039 Heat transfer for electronic equipment
An apparatus is provided that includes a planar heat conducting material that comprises a first heat sink conduction portion configured to conduct heat between...
US-9,379,038 Heat dissipation device and semiconductor device
Disclosed is a heat dissipation device which is reduced in the number of components, while having sufficient insulating function and cooling function with...
US-9,379,037 Thermal module accounting for increased board/die size in a portable computer
This application relates to a low profile, small footprint cooling stack that does not extend substantially beyond a footprint of an integrated circuit to which...
US-9,379,036 3DIC packages with heat dissipation structures
A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion...
US-9,379,035 IC package having non-horizontal die pad and lead frame therefor
A multi-component integrated circuit (IC) package has a base component (e.g., an interposer) defining a base of the IC package, a plurality of die pads...
US-9,379,034 Method of making an electronic device including two-step encapsulation and related devices
A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections...
US-9,379,033 Sensor package
A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface....
US-9,379,032 Semiconductor packaging having warpage control and methods of forming same
An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the...
US-9,379,031 Display panel for display device
Disclosed is a display panel in which a jumping wiring made of a heterogeneous material for the prevention of static electricity connects a signal pad with a...
US-9,379,030 Ion implantation method and ion implantation apparatus
Provided is an ion implantation method of transporting ions generated by an ion source to a wafer and implanting the ions into the wafer by irradiating an ion...
US-9,379,029 Inspection apparatus, inspection system, inspection method of semiconductor devices, and manufacturing method...
An inspection apparatus for inspecting output signal of a semiconductor device is provided with a monitor device configured to sense a signal on the monitor...
US-9,379,028 SOI CMOS structure having programmable floating backplate
SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually...
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