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Patent # Description
US-9,379,027 Method of utilizing trench silicide in a gate cross-couple construct
A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and...
US-9,379,026 Fin-shaped field-effect transistor process
A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second...
US-9,379,025 Method of forming source/drain contacts in unmerged FinFETs
A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. After forming replacement metal gate (RMG)...
US-9,379,024 Method for manufacturing a microelectronic device including depositing identical or different metallic layers...
A method for manufacturing a microelectronic device is provided, including forming a first semiconductor material layer on a first region of a top surface of a...
US-9,379,023 Semiconductor device with metal gate and high-k materials and method for fabricating the same
A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust...
US-9,379,022 Process for forming driver for normally on III-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode...
US-9,379,021 Method to reduce K value of dielectric layer for advanced FinFET formation
Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce...
US-9,379,020 Silicide formation on a wafer
A method of selective formation of silicide on a semiconductor wafer, wherein the metal layer is deposited over the entire wafer prior to application of the...
US-9,379,019 Methods of manufacturing a semiconductor device
In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An ARC layer is formed on the isolation layer pattern...
US-9,379,018 Increasing Ion/Ioff ratio in FinFETs and nano-wires
Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain...
US-9,379,017 Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark
A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over...
US-9,379,016 Wafer processing method
A wafer processing method including a wafer supporting step of attaching a front side of a dicing tape formed of synthetic resin to a back side of a wafer and...
US-9,379,015 Wafer processing method
A wafer processing method divides a wafer into individual devices along crossing streets formed on the front side of the wafer. The wafer has a substrate and a...
US-9,379,014 Static random-access memory (SRAM) array
A static random-access memory (SRAM) array includes a first metal layer and a second metal layer. The metal layer includes multiple first source lines spanning...
US-9,379,013 Method for forming a self-aligned contact in a damascene structure used to form a memory device
Exemplary embodiments of the present invention are directed towards a method for fabricating a self-aligned contact under a bitline in a damascene structure for...
US-9,379,012 Oxide mediated epitaxial nickel disilicide alloy contact formation
Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in...
US-9,379,011 Methods for depositing nickel films and for making nickel silicide and nickel germanide
In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide...
US-9,379,010 Methods for forming interconnect layers having tight pitch interconnect structures
Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form...
US-9,379,009 Interconnection structures in a semiconductor device and methods of manufacturing the same
Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a...
US-9,379,008 Metal PVD-free conducting structures
Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing...
US-9,379,007 Electromigration-resistant lead-free solder interconnect structures
Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes...
US-9,379,006 Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus
A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus...
US-9,379,005 Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
US-9,379,004 Semiconductor device with air gap and method for fabricating the same
A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a...
US-9,379,003 Semiconductor structures and methods of manufacturing the same
A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a...
US-9,379,002 Semiconductor device having air-gap
A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit...
US-9,379,001 Semiconductor device and method of fabricating the same
A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The...
US-9,379,000 Method for producing nanocarbon film and nanocarbon film
The present invention relates to a method for producing a nanocarbon film using a hybrid substrate with which a nanocarbon film free from defects can be...
US-9,378,999 Method for manufacturing SOI wafer
A method for manufacturing SOI wafer of forming an oxide film on a bond wafer of a semiconductor single crystal substrate, forming an ion implanted layer into...
US-9,378,998 Semiconductor structure and method of forming a harmonic-effect-suppression structure
A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor...
US-9,378,997 Substrate holding mechanism, substrate transporting device, and semiconductor manufacturing apparatus
A substrate holding mechanism includes a substrate holding claw for holding the substrate. The substrate holding claw includes a slant face for sliding the...
US-9,378,996 Holding device for holding a patterned wafer
This invention relates to a mounting apparatus for mounting and supporting one structure side of a substrate, which structure side has structures thereon. The...
US-9,378,995 Port door positioning apparatus and associated methods
A loadport has a port door and a frame with an opening through which the port door interfaces with a container door of a container for holding semiconductor...
US-9,378,994 Multi-position batch load lock apparatus and systems and methods including same
Various embodiments of batch load lock apparatus are disclosed. The batch load lock apparatus includes a load lock body including first and second load lock...
US-9,378,993 Wafer-related data management method and wafer-related data creation device
A wafer-related data creation device including a setting stand for setting wafer pallets, a test-use suction nozzle for picking up die on dicing sheet of a...
US-9,378,992 High throughput heated ion implantation system and method
An ion implantation system has an ion implantation apparatus coupled to first and second dual load lock assemblies, each having a respective first and second...
US-9,378,991 Substrate processing apparatus and substrate processing method
A substrate processing apparatus includes a transport chamber and a processing chamber that processes substrates. The transport chamber has a first substrate...
US-9,378,990 Adjusting intensity of laser beam during laser operation on a semiconductor device
Among other things, a system and method for adjusting the intensity of a laser beam applied to a semiconductor device are provided for herein. A sensor is...
US-9,378,989 Method and apparatus for cleaning semiconductor substrates
The present invention is related to a method and apparatus for cleaning a substrate, in particular a semiconductor substrate such as a silicon wafer. The...
US-9,378,988 Substrate processing apparatus and substrate processing method using processing solution
Nozzle arms for holding discharge heads are caused by a pivotal driving part to move between a processing position above a substrate and a standby position...
US-9,378,987 Semiconductor packages including gap in interconnection terminals and methods of manufacturing the same
A semiconductor package includes a lower package comprising a lower semiconductor chip mounted on a lower package substrate, an upper package comprising an...
US-9,378,986 Method for mounting a chip and chip package
Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate;...
US-9,378,985 Method of thinning a wafer to provide a raised peripheral edge
A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the...
US-9,378,984 Packaging a semiconductor device having wires with polymerized insulator skin
A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with...
US-9,378,983 Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is...
US-9,378,982 Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP)...
Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP)...
US-9,378,981 Thin film device and manufacturing method thereof
With a TFT using an oxide semiconductor film, there is such an issue that oxygen deficit is generated in a surface region of the oxide semiconductor film after...
US-9,378,980 Semiconductor device and method for manufacturing the same
A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor...
US-9,378,979 Methods of fabricating semiconductor devices and devices fabricated thereby
Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are...
US-9,378,978 Integrated oxide recess and floating gate fin trimming
Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods...
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