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Patent # Description
US-9,378,977 Non-volatile memory devices and methods of fabricating the same
A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode...
US-9,378,976 Method for forming interconnects
A conductive interconnect including trenches (110) and (186) and vias (202) are formed in a workpiece (100) by applying a dielectric film stack (120) over the...
US-9,378,975 Etching method to form spacers having multiple film layers
Methods herein can be used for removing silicon nitride around fins and other structures without damaging underlying silicon structures. Methods herein also...
US-9,378,974 Method for chemical polishing and planarization
A chemical planarization process described herein can be used for planarizing a substrate without using mechanical abrasion. A developable planarization...
US-9,378,973 Method of using sidewall image transfer process to form fin-shaped structures
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region;...
US-9,378,972 Integration of dense and variable pitch fin structures
Methods for forming semiconductor devices. Methods for forming fin structures include forming first sidewalls around a first set of mandrels. The first set of...
US-9,378,971 Technique to deposit sidewall passivation for high aspect ratio cylinder etch
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate...
US-9,378,970 Plasma etching process
A method and system are provided for etching a layer to be etched in a plasma etching reactor, including: forming a reactive layer by injection of at least one...
US-9,378,969 Low temperature gas-phase carbon removal
A method of etching carbon films on patterned heterogeneous structures is described and includes a gas phase etch using remote plasma excitation. The remote...
US-9,378,968 Method for planarizing semiconductor device
A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer...
US-9,378,967 Method of making a stacked microelectronic package
A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of...
US-9,378,966 Selective etching of silicon wafer
A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of...
US-9,378,965 Highly conductive source/drain contacts in III-nitride transistors
In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric...
US-9,378,964 Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus...
A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a...
US-9,378,963 Self-aligned contact and method of forming the same
Some embodiments of the present disclosure relate to a method to form a source/drain SAC for a transistor. The method comprises forming a pair of gate...
US-9,378,962 Nonvolatile semiconductor storage device having a charge storage layer that includes metal grains
A nonvolatile semiconductor storage device includes a semiconductor layer, a first insulating film formed on the semiconductor layer, a charge storage layer...
US-9,378,961 Methods of fabricating multiple gate stack compositions
A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over...
US-9,378,960 Method and structure for improved floating gate oxide integrity in floating gate semiconductor devices
Methods for forming floating gate transistors provide for using a self-aligned plug formed over a floating gate electrode without use of an additional...
US-9,378,959 Method of manufacturing insulated gate transistor semiconductor device
First, a first resist mask for forming an n.sup.+ emitter region is formed on the front surface of an n.sup.- semiconductor substrate. The first resist mask is...
US-9,378,958 Electrostatic discharge protection structure and fabricating method thereof
A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural...
US-9,378,957 Silicon substrates with doped surface contacts formed from doped silicon based inks and corresponding processes
The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline...
US-9,378,956 Wafer structure for electronic integrated circuit manufacturing
A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device...
US-9,378,955 Wafer structure for electronic integrated circuit manufacturing
A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device...
US-9,378,954 Plasma pre-treatment for improved uniformity in semiconductor manufacturing
Methods for forming a semiconductor devices are provided. A plasma pre-treatment operation is performed on a photoresist pattern formed over a material disposed...
US-9,378,953 Method for preparing polycrystalline metal oxide pattern
Disclosed is a method for preparing a polycrystalline metal oxide pattern, characterized by comprising: annealing a predetermined region of an amorphous metal...
US-9,378,952 Tall relaxed high percentage silicon germanium fins on insulator
A method is provided for forming tall silicon germanium alloy fin structures on a surface of an insulator layer. The silicon germanium alloy fin structures have...
US-9,378,951 Laser annealing apparatus and method of manufacturing display apparatus using the same
A method of manufacturing a display apparatus, the method including forming an amorphous silicon layer on a substrate, placing the substrate with the amorphous...
US-9,378,950 Methods for removing nuclei formed during epitaxial growth
A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor...
US-9,378,949 Monolithic integration of group III nitride epitaxial layers
A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the...
US-9,378,948 FinFET structures having silicon germanium and silicon fins
A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon...
US-9,378,947 Buffer layer deposition for thin-film solar cells
Improved methods and apparatus for forming thin-film buffer layers of chalcogenide on a substrate web. Solutions containing the reactants for the buffer layer...
US-9,378,946 Silicon substrates with compressive stress and methods for production of the same
A heterostructure including: a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate...
US-9,378,944 Method and apparatus of forming carbon film
According to an embodiment of present disclosure, a method of forming a carbon film on a substrate to be processed is provided. The method includes loading a...
US-9,378,943 Method of manufacturing semiconductor device, method of processing substrate substrate processing apparatus and...
An insulating film including characteristics such as low permittivity, a low etching rate and a high insulation property is formed. Supplying a gas containing...
US-9,378,942 Deposition method and deposition apparatus
Disclosed is a method for depositing an insulating film with a high coverage through a low temperature process. The deposition method deposits an insulating...
US-9,378,941 Interface treatment of semiconductor surfaces with high density low energy plasma
An electron beam plasma source is used in a soft plasma surface treatment of semiconductor surfaces containing Ge or group III-V compound semiconductor materials.
US-9,378,940 Substrate processing apparatus and substrate processing method
The present disclosure provides a substrate processing apparatus including: a substrate processing chamber configured to process a substrate on which a target...
US-9,378,939 Electric lamp and manufacture method therefor
A high pressure gas discharge lamp includes a ceramic discharge vessel that has a container wall enclosing a discharge space having a filling. First and second...
US-9,378,938 Reproducibility of impact-based ionization source for low and high organic mobile phase compositions using a...
An ion source is disclosed comprising one or more nebulizers and one or more mesh or grid targets. The one or more nebulizers are arranged and adapted to emit,...
US-9,378,937 Mass spectrometer and liquid-metal ion source for a mass spectrometer of this type
A mass spectrometer includes an ion source for producing a primary ion beam, which has a heatable ion emitter coated by a liquid metal layer essentially...
US-9,378,936 Fast switching, dual polarity, dual output high voltage power supply
Systems, devices, circuits, and methods are provided for an improved mass spectrometry detection system that comprises an ion source and a detector that operate...
US-9,378,935 Geiger-Muller counter tube and radiation measurement apparatus
A Geiger-Muller counter tube includes a cylindrical enclosing tube, an anode electrode, a cylindrical cathode electrode, an inert gas, and a quenching gas. The...
US-9,378,934 Racetrack-shaped magnetic-field-generating apparatus for magnetron sputtering
A racetrack-shaped magnetic-field-generating apparatus for magnetron sputtering having a linear portion and corner portions, which comprises a center magnetic...
US-9,378,933 Apparatus for generating reactive gas with glow discharges and methods of use
An apparatus for generating a flow of reactive gas for decontaminating a material, surface or area, which comprises a first electrode member comprising a first...
US-9,378,932 Device and process for preventing substrate damages in a DBD plasma installation
The present invention relates to a process for preventing substrate damages in an installation for surface treatment by dielectric barrier discharge (DBD) and a...
US-9,378,931 Pulse plasma apparatus and drive method thereof
A pulse plasma apparatus includes a process chamber, source RF generator configured to supply first and second level RF pulse power having first and second duty...
US-9,378,930 Inductively coupled plasma reactor having RF phase control and methods of use thereof
Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the...
US-9,378,929 Plasma processing apparatus and plasma processing method
A plasma processing apparatus is offered which has evacuable vacuum vessel, processing chamber disposed inside the vacuum vessel and having inside space in...
US-9,378,928 Apparatus for treating a gas in a conduit
Apparatus for treating a gas in a conduit of a substrate processing system are provided. In some embodiments, an apparatus for treating a gas in a conduit of a...
US-9,378,927 AutoSlice and view undercut method
A method is provided for slice and view processing of samples with dual beam systems. The slice and view processing includes providing a location for particles...
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