At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Buffering systems for accessing multiple layers of memory in integrated
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for...
Memory system and operation method thereof
A memory system includes a memory device having a plurality of memory blocks, each including a plurality of pages, each page including a plurality of memory...
Programming a memory cell to a voltage to indicate a data value and after
a relaxation time programming the...
A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is...
Method for programming selected memory cells in nonvolatile memory device
and nonvolatile memory device thereof
A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels...
Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells
Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In...
Nonvolatile memory device and worldline driving method thereof
According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a...
Electronic device and method for operating the same
An electronic device including a semiconductor memory. The semiconductor memory includes a cell array divided into at least two regions each of which includes a...
Apparatuses and operation methods associated with resistive memory cell
arrays with separate select lines
The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data...
Variable resistance nonvolatile memory element writing method and variable
resistance nonvolatile memory device
A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element,...
Variable resistance memory devices and erase verifying methods thereof
An erase verifying method includes applying a first voltage to a plurality of word lines connected to a memory cell block, and applying a second voltage less...
Resistive memory device capable of increasing sensing margin by
controlling interface states of cell transistors
A resistive memory device includes a memory cell array having a plurality of memory cells therein, which operate in response to word line driving and column...
Sense amplifier local feedback to control bit line voltage
Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for...
Resistive memory device, method of fabricating the same, and memory
apparatus and data processing system having...
A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system...
Non-volatile memory using bi-directional resistive elements
A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive...
Methods of operating variable resistance memory devices
A method of operating a resistive non-volatile memory can be provided by applying a forming voltage across first and second electrodes of a selected memory cell...
Systems and methods for last written page handling in a memory device
Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one...
Relaxing verification conditions in memory programming and erasure
A method for data storage includes setting a plurality of memory cells to hold respective target analog values, by applying to the memory cells a sequence of...
Pulse width modulation device
A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N...
Non-volatile static random access memory circuits
A non-volatile static random access memory (nvSRAM) circuit is provided. The nvSRAM circuit includes first and second switches and a latch circuit. The first...
Boosting voltage level
A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply...
Stable memory source bias over temperature and method
Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic...
The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a...
System and method to regulate operating voltage of a memory array
A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an...
Oscillator and memory device including the same
An oscillator includes a comparison means suitable for generating a comparison signal by comparing an internal voltage of an internal node with a reference...
Semiconductor memory device
A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are...
Memory controller and associated signal generating method
The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command...
Semiconductor device having a memory and calibration circuit that adjusts
output buffer impedance dependent...
A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically...
Method of writing to a spin torque magnetic random access memory
A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample...
Provide a memory device capable of increasing performance by performing a
write operation using stable multi...
A voltage generator comprises a reference voltage providing unit, a comparison voltage providing unit and a comparison unit. The reference voltage providing...
Method for writing to a magnetic tunnel junction device
A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying...
Mismatch and noise insensitive sense amplifier circuit for STT MRAM
A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is...
Storage element and memory
A storage element includes a magnetization fixed layer, and a magnetization free layer. The magnetization fixed layer includes a plurality of ferromagnetic...
Integrated MRAM module
Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache...
Method of writing to a spin torque magnetic random access memory
A method for determining an optimized write pattern for low write error rate operation of a spin torque magnetic random access memory. The method provides a way...
Apparatuses and methods for controlling a clock signal provided to a clock
Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command...
Apparatus and method for buffered write commands in a memory
Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after...
Voltage level shifted self-clocked write assistance
Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input...
Negative bitline write assist circuit and method for operating the same
A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write...
Memory controllers, systems, and methods supporting multiple request modes
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over...
Memory controller with phase adjusted clock for performing memory
In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and...
Resistive random-access memory devices
A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the...
Security device using high latency memory to implement high update rate
statistics for large number of events
A security device includes a controller configured to determine a flow identifier and an event counter associated with a received data packet and a counter...
I/O circuit with phase mixer for slew rate control
An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state...
Apparatus with write-back buffer and associated methods
An apparatus comprises a source to communicate data, and a storage circuit to store data communicated by the source. The apparatus further comprises a...
System, apparatus, and method for sense amplifiers
An offset cancelling sense amplifier according to some examples of the disclosure may use a double sensing margin structure and positive feedback to achieve...
The present disclosure provides a sense amplifier. The sense amplifier includes a first inverting circuit, a second inverting circuit, a pre-charge circuit, a...
System and method for automatic detection of power up for a dual-rail
A dual-rail memory circuit having a sleep generation circuit configured to prevent undesired currents from being generated during power-up and while...
Package including a plurality of stacked semiconductor devices including a
capacitance enhanced through via and...
A plurality of semiconductor memory devices on a multi-chip package is disclosed. Each semiconductor device may include a plurality of through vias and a...
Back gate bias voltage control of oxide semiconductor transistor
To stably control a threshold voltage of a functional circuit using an oxide semiconductor. A variable bias circuit, a monitoring oxide semiconductor transistor...
Semiconductor device, electronic component, and electronic device
A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is...